Mark Po-Hung Lin

65 papers A* 11A 12Journal 22Unranked 20
YearRankTypeTitle / Venue / Authors
2025 — conf
Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning.
MLCAD
Chun-Yen Huang, Hsuan-I Chen, Hao-Wen Ho, Pei-Hsin Kang, Mark Po-Hung Lin, Wen-Hao Liu, Haoxing Ren
2024 — conf
Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids.
ISPD
Mark Po-Hung Lin, Chou-Chen Lee, Yi-Chao Hsieh
2024 J jnl
SSIOE: Self-Supervised Indoor Occupancy Estimation for Intelligent Building Management.
IEEE Trans Autom. Sci. Eng.
Sin-Han Huang, Tzu-Yin Chao, Beatrice Adelaide Wibisono, Mark Po-Hung Lin, Ching-Chun Huang
2024 A* conf
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs.
DAC
Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin
2023 A* conf
Late Breaking Results: PVT-Sensitive Delay Fitting for High-Performance Computing.
DAC
Ding-Hao Wang, Shuo-Hung Hsu, Shu-Hsiang Yang, Pei-Ju Lin, Hui-Ting Yang, Mark Po-Hung Lin
2023 — conf
Layout Synthesis of Analog Primitive Cells with Variational Autoencoder.
SMACD
Po-Chun Wang, Mark Po-Hung Lin, Chien-Nan Jimmy Liu, Hung-Ming Chen
2023 — conf
On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC.
ASP-DAC
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
2023 J jnl
On Reducing LDE Variations in Modern Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen
2023 J jnl
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen
2022 — conf
Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning.
MLCAD
Hung-Yun Hsu, Mark Po-Hung Lin
2022 — conf
Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead.
ASP-DAC
Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
2022 — conf
On Optimizing Capacitor Array Design for Advanced Node SAR ADC.
SMACD
Cheng-Yu Chiang, Chia-Lin Hu, Kang-Yu Chang, Mark Po-Hung Lin, Shyh-Jye Jou, Hung-Yu Chen, Chien-Nan Jimmy Liu, Hung-Ming Chen
2021 A* conf
A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths.
DAC
Ding-Hao Wang, Pei-Ju Lin, Hui-Ting Yang, Ching-An Hsu, Sin-Han Huang, Mark Po-Hung Lin
2021 — conf
A Novel Technology Mapper for Complex Universal Gates.
ASP-DAC
Meng-Che Wu, Ai Quoc Dao, Mark Po-Hung Lin
2021 — conf
Massive Figure Extraction and Classification in Electronic Component Datasheets for Accelerating PCB Design Preparation.
MLCAD
Kuan-Chun Chen, Chou-Chen Lee, Mark Po-Hung Lin, Yan-Jhih Wang, Yi-Ting Chen
2020 A conf
Achieving Analog Layout Integrity through Learning and Migration Invited Talk.
ICCAD
Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen
2020 J jnl
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yen-Yu Su, Shuo-Hui Wang, Wei-Liang Wu, Mark Po-Hung Lin
2020 A* conf
Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design.
DAC
Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin
2020 A* conf
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization.
DAC
Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin
2020 A conf
Overview of 2020 CAD Contest at ICCAD.
ICCAD
Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin
2019 A conf
IR-aware Power Net Routing for Multi-Voltage Mixed-Signal Design.
DATE
Shuo-Hui Wang, Guan-Hong Liou, Yen-Yu Su, Mark Po-Hung Lin
2019 A conf
Overview of 2019 CAD Contest at ICCAD.
ICCAD
Ulf Schlichtmann, Sabya Das, Ing-Chao Lin, Mark Po-Hung Lin
2018 — conf
Classifying Analog and Digital Circuits with Machine Learning Techniques Toward Mixed-Signal Design Automation.
SMACD
Guan-Hong Liou, Shuo-Hui Wang, Yan-Yu Su, Mark Po-Hung Lin
2018 A* conf
Efficient computation of ECO patch functions.
DAC
Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
2018 J jnl
SAT-Based Fault Equivalence Checking in Functional Safety Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko
2017 — conf
AIsim: Functional Simulator for Analog-to-Information Perceptual Systems.
ISVLSI
Hong Liu, Zheyu Liu, Fei Qiao, Mark Po-Hung Lin, Qi Wei, Huazhong Yang
2017 J jnl
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017 A conf
High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC.
DATE
Nai-Chen Chen, Pang-Yen Chou, Helmut E. Graeb, Mark Po-Hung Lin
2017 J jnl
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters.
IEEE Trans. Very Large Scale Integr. Syst.
Pang-Yen Chou, Nai-Chen Chen, Mark Po-Hung Lin, Helmut Graeb
2017 J jnl
Minimizing detection-to-boosting latency toward low-power error-resilient circuits.
Integr.
Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin
2017 J jnl
Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing.
CoRR
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2017 J jnl
Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen
2017 A conf
State retention for power gated design with non-uniform multi-bit retention latches.
ICCAD
Guo-Gin Fan, Mark Po-Hung Lin
2016 J jnl
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Po-Hsun Chang, Shuenn-Yuh Lee, Helmut E. Graeb
2016 — conf
Latch Clustering for Minimizing Detection-to-Boosting Latency Toward Low-Power Resilient Circuits.
SLIP
Chih-Cheng Hsu, Mark Po-Hung Lin, Masanori Hashimoto
2016 A* conf
Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.
DAC
Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann
2016 J jnl
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching.
ACM Trans. Design Autom. Electr. Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho
2016 — conf
Recent research development and new challenges in analog layout synthesis.
ASP-DAC
Mark Po-Hung Lin, Yao-Wen Chang, Chih-Ming Hung
2015 J jnl
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho
2015 — conf
Analog layout synthesis with knowledge mining.
ECCTD
Po-Hsun Wu, Mark Po-Hung Lin, Tsung-Yi Ho
2015 J jnl
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen
2015 — conf
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment.
ISPD
Po-Hsun Wu, Mark Po-Hung Lin, Xin Li, Tsung-Yi Ho
2015 J jnl
Crosstalk-aware multi-bit flip-flop generation for power optimization.
Integr.
Chih-Cheng Hsu, Mark Po-Hung Lin, Yao-Tsung Chang
2015 — conf
Low-power gated clock tree optimization for three-dimensional integrated circuits.
VLSI-DAT
Yu-Chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin
2014 J jnl
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Tsung-Yi Ho, Bin-Da Liu
2014 A conf
More effective power-gated circuit optimization with multi-bit retention registers.
ICCAD
Shu-Hung Lin, Mark Po-Hung Lin
2014 A* conf
Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.
DAC
Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin
2014 — conf
Power optimization for clock network with clock gate cloning and flip-flop merging.
ISPD
Shih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin
2013 J jnl
1-D Cell Generation With Printability Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen, Shun-Ren Siao, Shu-Hung Lin
2013 J jnl
Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Yi-Ting He, Vincent Wei-Hao Hsiao, Rong-Guey Chang, Shuenn-Yuh Lee
2013 A conf
In-placement clock-tree aware multi-bit flip-flop generation for power optimization.
ICCAD
Chih-Cheng Hsu, Yu-Chuan Chen, Mark Po-Hung Lin
2013 — conf
Lithography-aware 1-dimensional cell generation.
ECCTD
Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho, Yu-Chuan Chen
2012 — conf
Crosstalk-aware power optimization with multi-bit flip-flops.
ASP-DAC
Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin
2012 A conf
Performance-driven analog placement considering monotonic current paths.
ICCAD
Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu
2011 A conf
A corner stitching compliant B
ICCAD
Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu
2011 J jnl
Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist.
Microelectron. J.
Shuenn-Yuh Lee, Chih-Yuan Chen, Jia-Hua Hong, Rong-Guey Chang, Mark Po-Hung Lin
2011 J jnl
Post-Placement Power Optimization With Multi-Bit Flip-Flops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang
2011 — conf
Recent research in analog placement considering thermal gradient.
ECCTD
Mark Po-Hung Lin
2011 J jnl
Thermal-Driven Analog Placement Considering Device Matching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2010 A conf
Post-placement power optimization with multi-bit flip-flops.
ICCAD
Yao-Tsung Chang, Chih-Cheng Hsu, Mark Po-Hung Lin, Yu-Wen Tsai, Sheng-Fong Chen
2009 J jnl
Analog Placement Based on Symmetry-Island Formulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Po-Hung Lin, Yao-Wen Chang, Shyh-Chang Lin
2009 A conf
Analog layout synthesis - Recent advances in topological approaches.
DATE
Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser
2009 A* conf
Thermal-driven analog placement considering device matching.
DAC
Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang
2008 A* conf
Analog placement based on hierarchical module clustering.
DAC
Mark Po-Hung Lin, Shyh-Chang Lin
2007 A* conf
Analog Placement Based on Novel Symmetry-Island Formulation.
DAC
Mark Po-Hung Lin, Shyh-Chang Lin