Mark Kassab - RankMe

46 papers A* 3A 18B 2Misc 3Journal 11Unranked 8

Year	Rank	Type	Title / Venue / Authors
2022	Misc	`conf`	Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy
2022	J	`jnl`	Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chong-Siao Ye, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski
2020	Misc	`conf`	Effective Design of Layout-Friendly EDT Decompressor. VTS Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer
2020	B	`conf`	Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski
2020	—	`conf`	Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng
2020	A	`conf`	Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada
2020	A	`conf`	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant
2019	—	`conf`	TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
2015	—	`conf`	Hybrid Hierarchical and Modular Tests for SoC Designs. NATW Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski
2015	J	`jnl`	Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2015	J	`jnl`	Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	J	`jnl`	Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2014	A	`conf`	Isometric test compression with low toggling activity. ITC Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang
2014	—	`conf`	Test Compression Improvement with EDT Channel Sharing in SoC Designs. NATW Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung
2014	—	`ch.`	Timing-Aware ATPG. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin
2014	B	`conf`	Using dynamic shift to reduce test data volume in high-compression designs. ETS Xijiang Lin, Mark Kassab, Janusz Rajski
2013	A	`conf`	EDT bandwidth management - Practical scenarios for large SoC designs. ITC Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles
2013	J	`jnl`	Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2012	J	`jnl`	EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
2011	A	`conf`	A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. ITC Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
2011	A	`conf`	EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski
2010	Misc	`conf`	At-speed scan test with low switching activity. VTS Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab
2010	A	`conf`	Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
2010	A	`conf`	Dynamic channel allocation for higher EDT compression in SoC designs. ITC Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
2010	A	`conf`	Low capture power at-speed test in EDT environment. ITC Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
2009	J	`jnl`	Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2009	—	`conf`	Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium Xijiang Lin, Mark Kassab
2008	A	`conf`	Low Power Scan Shift and Capture in the EDT Environment. ITC Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
2008	J	`jnl`	X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2007	—	`conf`	Test Generation for Timing-Critical Transition Faults. ATS Xijiang Lin, Mark Kassab, Janusz Rajski
2007	A*	`conf`	Test Generation in the Presence of Timing Exceptions and Constraints. DAC Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
2007	J	`jnl`	X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai
2006	—	`conf`	At-Speed Testing with Timing Exceptions and Constraints-Case Studies. ATS Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo
2006	A	`conf`	OCI: Open Compression Interface. ITC Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie
2006	—	`conf`	Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
2006	A	`conf`	X-Press Compactor for 1000x Reduction of Test Data. ITC Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab
2004	A	`conf`	Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
2004	J	`jnl`	Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
2004	A	`conf`	Realizing High Test Quality Goals with Smart Test Resource Usage. ITC Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
2003	J	`jnl`	Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
2003	A	`conf`	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
2002	A	`conf`	Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
1999	A	`conf`	Logic BIST for large industrial designs: real issues and case studies. ITC Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
1998	A*	`conf`	A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
1995	A	`conf`	Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC Mark Kassab, Janusz Rajski, Jerzy Tyszer
1995	A*	`conf`	Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer