Mark Horowitz

231 papers A* 56A 19B 10C 7Misc 2Journal 97Unranked 38
YearRankTypeTitle / Venue / Authors
2026 J jnl
Onyx: A 12-nm Programmable Accelerator for Dense and Sparse Applications.
IEEE J. Solid State Circuits
Kalhan Koul, Olivia Hsu, Yuchen Mei, Sai Gautham Ravipati, Maxwell Strange, Jackson Melchert, Alex Carsello, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Zhouhua Xie, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2025 A* conf
A Probabilistic Perspective on Tiling Sparse Tensor Algebra.
MICRO
Ritvik Sharma, Zi Yu Xue, Nathan Zhang, Rubens Lacouture, Fredrik Kjolstad, Sara Achour, Mark Horowitz
2025 A conf
Application of Formal Methods (SAT/SMT) to the Design of Constrained Codes.
DATE
Sunil Sudhakaran, Clark W. Barrett, Mark Horowitz
2025 J jnl
Designing Programmable Accelerators for Sparse Tensor Algebra.
IEEE Micro
Kalhan Koul, Zhouhua Xie, Maxwell Strange, Sai Gautham Ravipati, Bo-Wun Cheng, Olivia Hsu, Po-Han Chen, Mark Horowitz, Fredrik Kjolstad, Priyanka Raina
2025 J jnl
Opal: A 16-nm Coarse-Grained Reconfigurable Array SoC for Full Sparse Machine Learning Applications.
IEEE Solid State Circuits Lett.
Po-Han Chen, Bo-Wun Cheng, Michael Oduoza, Zhouhua Xie, Rupert Lu, Sai Gautham Ravipati, Kalhan Koul, Alex Carsello, Yuchen Mei, Mark Horowitz, Priyanka Raina
2025 — conf
Opal: A 16nm Coarse-Grained Reconfigurable Array for Full Sparse ML Applications.
CICC
Po-Han Chen, Bo-Wun Cheng, Michael Oduoza, Zhouhua Xie, Kalhan Koul, Sai Gautham Ravipati, Yuchen Mei, Rupert Lu, Alex Carsello, Mark Horowitz, Priyanka Raina
2024 J jnl
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits
Kathleen Feng, Taeyoung Kong, Kalhan Koul, Jackson Melchert, Alex Carsello, Qiaoyi Liu, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Christopher Torng, Mark Horowitz, Priyanka Raina
2024 J jnl
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina
2024 — conf
Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications.
VLSI Technology and Circuits
Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2024 — conf
Onyx: A Programmable Accelerator for Sparse Tensor Algebra.
HCS
Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina
2024 B conf
Vision Transformer Computation and Resilience for Dynamic Inference.
ISPASS
Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
2023 J jnl
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst.
Kalhan Koul, Jackson Melchert, Kavya Sreedhar, Leonard Truong, Gedeon Nyengele, Keyi Zhang, Qiaoyi Liu, Jeff Setter, Po-Han Chen, Yuchen Mei, Maxwell Strange, Ross Daly, Caleb Donovick, Alex Carsello, Taeyoung Kong, Kathleen Feng, Dillon Huff, Ankita Nayak, Rajsekhar Setaluri, James Thomas, Nikhil Bhagdikar, David Durst, Zachary A. Myers, Nestan Tsiskaridze, Stephen Richardson, Rick Bahr, Kayvon Fatahalian, Pat Hanrahan, Clark W. Barrett, Mark Horowitz, Christopher Torng, Fredrik Kjolstad, Priyanka Raina
2023 J jnl
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.
IEEE Comput. Archit. Lett.
Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina
2023 J jnl
Hardware Abstractions and Hardware Mechanisms to Support Multi-Task Execution on Coarse-Grained Reconfigurable Arrays.
CoRR
Taeyoung Kong, Kalhan Koul, Priyanka Raina, Mark Horowitz, Christopher Torng
2023 J jnl
Higher education's influence on social networks and entrepreneurship in Brazil.
Soc. Netw. Anal. Min.
Michelle Reddy, Júlio C. Nardelli, Yuri L. Pereira, Leonardo B. Oliveira, Thiago H. Silva, Marisa Vasconcelos, Mark Horowitz
2023 J jnl
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.
ACM Trans. Reconfigurable Technol. Syst.
Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Christopher Torng, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina
2023 J jnl
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators.
ACM Trans. Archit. Code Optim.
Qiaoyi Liu, Jeff Setter, Dillon Huff, Maxwell Strange, Kathleen Feng, Mark Horowitz, Priyanka Raina, Fredrik Kjolstad
2022 J jnl
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst.
Kavya Sreedhar, Mark Horowitz, Christopher Torng
2022 — conf
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
VLSI Technology and Circuits
Alex Carsello, Kathleen Feng, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina
2022 — conf
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration.
HCS
Kathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary A. Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina
2022 J jnl
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Steven Herbst, Gabriel Rutsch, Wolfgang Ecker, Mark Horowitz
2022 J jnl
Bringing Source-Level Debugging Frameworks to Hardware Generators.
CoRR
Keyi Zhang, Zain Asgar, Mark Horowitz
2022 A* conf
Bringing source-level debugging frameworks to hardware generators.
DAC
Keyi Zhang, Zain Asgar, Mark Horowitz
2022 J jnl
Canal: A Flexible Interconnect Generator for Coarse-Grained Reconfigurable Arrays.
CoRR
Jackson Melchert, Keyi Zhang, Yuchen Mei, Mark Horowitz, Christopher Torng, Priyanka Raina
2022 J jnl
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays.
CoRR
Jackson Melchert, Yuchen Mei, Kalhan Koul, Qiaoyi Liu, Mark Horowitz, Priyanka Raina
2022 J jnl
Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications.
CoRR
Kavya Sreedhar, Jason Clemons, Rangharajan Venkatesan, Stephen W. Keckler, Mark Horowitz
2022 J jnl
The Sparse Abstract Machine.
CoRR
Olivia Hsu, Maxwell Strange, Jaeyeon Won, Ritvik Sharma, Kunle Olukotun, Joel S. Emer, Mark Horowitz, Fredrik Kjolstad
2022 A* conf
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.
DAC
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng
2021 J jnl
Automated Design Space Exploration of CGRA Processing Element Architectures using Frequent Subgraph Analysis.
CoRR
Jackson Melchert, Kathleen Feng, Caleb Donovick, Ross Daly, Clark W. Barrett, Mark Horowitz, Pat Hanrahan, Priyanka Raina
2021 B conf
Automating System Configuration.
FMCAD
Nestan Tsiskaridze, Maxwell Strange, Makai Mann, Kavya Sreedhar, Qiaoyi Liu, Mark Horowitz, Clark W. Barrett
2021 J jnl
Automating System Configuration.
CoRR
Nestan Tsiskaridze, Maxwell Strange, Makai Mann, Kavya Sreedhar, Qiaoyi Liu, Mark Horowitz, Clark W. Barrett
2021 J jnl
Compiling Halide Programs to Push-Memory Accelerators.
CoRR
Qiaoyi Liu, Dillon Huff, Jeff Setter, Maxwell Strange, Kathleen Feng, Kavya Sreedhar, Ziheng Wang, Keyi Zhang, Mark Horowitz, Priyanka Raina, Fredrik Kjolstad
2021 J jnl
Enabling Reusable Physical Design Flows with Modular Flow Generators.
CoRR
Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng
2021 J jnl
Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions.
IACR Cryptol. ePrint Arch.
Kavya Sreedhar, Mark Horowitz, Christopher Torng
2020 A conf
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs.
DATE
Ankita Nayak, Keyi Zhang, Rajsekhar Setaluri, Alex Carsello, Makai Mann, Stephen Richardson, Rick Bahr, Pat Hanrahan, Mark Horowitz, Priyanka Raina
2020 A* conf
Creating an Agile Hardware Design Flow.
DAC
Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang
2020 J jnl
Fast FPGA emulation of analog dynamics in digitally-driven systems.
CoRR
Steven Herbst, ByongChan Lim, Mark Horowitz
2020 A* conf
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.
ASPLOS
Xuan Yang, Mingyu Gao, Qiaoyi Liu, Jeff Setter, Jing Pu, Ankita Nayak, Steven Bell, Kaidi Cao, Heonjae Ha, Priyanka Raina, Christos Kozyrakis, Mark Horowitz
2020 — conf
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.
VLSI Circuits
Sung-Jin Kim, Zachary A. Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
2020 J jnl
Open-Source Synthesizable Analog Blocks for High-Speed Link Designs: 20-GS/s 5b ENOB Analog-to-Digital Converter and 5-GHz Phase Interpolator.
CoRR
Sung-Jin Kim, Zachary A. Myers, Steven Herbst, ByongChan Lim, Mark Horowitz
2020 A conf
SegAlign: a scalable GPU-based whole genome aligner.
SC
Sneha D. Goenka, Yatish Turakhia, Benedict Paten, Mark Horowitz
2020 J jnl
fault: A Python Embedded Domain-Specific Language For Metaprogramming Portable Hardware Verification Components.
CoRR
Lenny Truong, Steven Herbst, Rajsekhar Setaluri, Makai Mann, Ross G. Daly, Keyi Zhang, Caleb Donovick, Daniel Stanley, Mark Horowitz, Clark W. Barrett, Pat Hanrahan
2020 — conf
fault: A Python Embedded Domain-Specific Language for Metaprogramming Portable Hardware Verification Components.
CAV (1)
Lenny Truong, Steven Herbst, Rajsekhar Setaluri, Makai Mann, Ross G. Daly, Keyi Zhang, Caleb Donovick, Daniel Stanley, Mark Horowitz, Clark W. Barrett, Pat Hanrahan
2019 J jnl
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification.
IEEE Trans. Very Large Scale Integr. Syst.
ByongChan Lim, Mark Horowitz
2019 J jnl
Dataset Culling: Towards Efficient Training Of Distillation-Based Domain Specific Models.
CoRR
Kentaro Yoshioka, Edward Lee, Simon Wong, Mark Horowitz
2019 B conf
Dataset Culling: Towards Efficient Training of Distillation-Based Domain Specific Models.
ICIP
Kentaro Yoshioka, Edward Lee, Simon Wong, Mark Horowitz
2019 B conf
Falcon - A Flexible Architecture For Accelerating Cryptography.
MASS
Kevin Kiningham, Philip Alexander Levis, Mark Anderson, Dan Boneh, Mark Horowitz, Maurice Shih
2019 J jnl
StartupBR: Higher Education's Influence on Social Networks and Entrepreneurship in Brazil.
CoRR
Michelle Reddy, Júlio C. Nardelli, Yuri L. Pereira, Marisa Vasconcelos, Thiago Henrique Silva, Leonardo B. Oliveira, Mark Horowitz
2019 A* conf
TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators.
ASPLOS
Mingyu Gao, Xuan Yang, Jing Pu, Mark Horowitz, Christos Kozyrakis
2018 — book
Compiling Algorithms for Heterogeneous Systems
Steven Bell, Jing Pu, James Hegarty, Mark Horowitz
2018 J jnl
DNN Dataflow Choice Is Overrated.
CoRR
Xuan Yang, Mingyu Gao, Jing Pu, Ankita Nayak, Qiaoyi Liu, Steven Bell, Jeff Setter, Kaidi Cao, Heonjae Ha, Christos Kozyrakis, Mark Horowitz
2018 A conf
Fast FPGA emulation of analog dynamics in digitally-driven systems.
ICCAD
Steven Herbst, ByongChan Lim, Mark Horowitz
2018 J jnl
Mapping Histological Slice Sequences to the Allen Mouse Brain Atlas Without 3D Reconstruction.
Frontiers Neuroinformatics
Jing Xiong, Jing Ren, Liqun Luo, Mark Horowitz
2018 — conf
Tethys: Collecting Sensor Data without Infrastracture or Trust.
IoTDI
Holly Chiang, James Hong, Kevin Kiningham, Laurynas Riliskis, Philip Alexander Levis, Mark Horowitz
2018 J jnl
Training Domain Specific Models for Energy-Efficient Object Detection.
CoRR
Kentaro Yoshioka, Edward Lee, Mark Horowitz
2017 J jnl
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era.
IEEE Des. Test
Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, Shahar Kvatinsky
2017 J jnl
Programming Heterogeneous Systems from an Image Processing DSL.
ACM Trans. Archit. Code Optim.
Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, Mark Horowitz
2017 A* conf
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory.
ASPLOS
Mingyu Gao, Jing Pu, Xuan Yang, Mark Horowitz, Christos Kozyrakis
2016 — conf
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture.
VLSI Circuits
Suyao Ji, Jing Pu, ByongChan Lim, Mark Horowitz
2016 J jnl
A Systematic Approach to Blocking Convolutional Neural Networks.
CoRR
Xuan Yang, Jing Pu, Blaine Burton Rister, Nikhil Bhagdikar, Stephen Richardson, Shahar Kvatinsky, Jonathan Ragan-Kelley, Ardavan Pedram, Mark Horowitz
2016 B conf
CESEL: Securing a Mote for 20 Years.
EWSN
Kevin Kiningham, Mark Horowitz, Philip Alexander Levis, Dan Boneh
2016 J jnl
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era.
CoRR
Ardavan Pedram, Stephen Richardson, Sameh Galal, Shahar Kvatinsky, Mark Horowitz
2016 — conf
Deep compression and EIE: Efficient inference engine on compressed deep neural network.
Hot Chips Symposium
Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark Horowitz, Bill Dally
2016 J jnl
Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models.
IEEE Trans. Circuits Syst. I Regul. Pap.
ByongChan Lim, Mark Horowitz
2016 A* conf
Evaluating programmable architectures for imaging and vision applications.
MICRO
Artem Vasilyev, Nikhil Bhagdikar, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016 J jnl
FPMax: a 106GFLOPS/W at 217GFLOPS/mm2 Single-Precision FPU, and a 43.7GFLOPS/W at 74.6GFLOPS/mm2 Double-Precision FPU, in 28nm UTBB FDSOI.
CoRR
Jing Pu, Sameh Galal, Xuan Yang, Ofer Shacham, Mark Horowitz
2016 A* conf
Improving energy efficiency of DRAM by exploiting half page row access.
MICRO
Heonjae Ha, Ardavan Pedram, Stephen Richardson, Shahar Kvatinsky, Mark Horowitz
2016 J jnl
Programming Heterogeneous Systems from an Image Processing DSL.
CoRR
Jing Pu, Steven Bell, Xuan Yang, Jeff Setter, Stephen Richardson, Jonathan Ragan-Kelley, Mark Horowitz
2016 J jnl
Rigel: flexible multi-rate image processing hardware.
ACM Trans. Graph.
James Hegarty, Ross G. Daly, Zachary DeVito, Mark Horowitz, Pat Hanrahan, Jonathan Ragan-Kelley
2016 J jnl
Tomographic Reconstruction and Alignment Using Matrix Norm Minimization.
IEEE J. Sel. Top. Signal Process.
Kahye Song, Mark Horowitz
2015 J jnl
Building Conflict-Free FFT Schedules.
IEEE Trans. Circuits Syst. I Regul. Pap.
Stephen Richardson, Dejan Markovic, Andrew Danowitz, John S. Brunhaver, Mark Horowitz
2015 J jnl
Convolution engine: balancing efficiency and flexibility in specialized computing.
Commun. ACM
Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark Horowitz
2015 Misc conf
Demo: Tethys - An Energy Harvesting Networked Water Flow Sensor.
SenSys
Holly Chiang, James Hong, Kevin Kiningham, Jiaqi Xue, Laurynas Riliskis, Philip Alexander Levis, Mark Horowitz
2015 J jnl
Digital Analog Design: Enabling Mixed-Signal System Validation.
IEEE Des. Test
ByongChan Lim, Ji-Eun Jang, James Mao, Jaeha Kim, Mark Horowitz
2015 B conf
Scale- and orientation-invariant keypoints in higher-dimensional data.
ICIP
Blaine Rister, Daniel Reiter, Hejia Zhang, Daniel Volz, Mark Horowitz, Refaat E. Gabr, Joseph R. Cavallaro
2014 — conf
1.1 Computing's energy problem (and what we can do about it).
ISSCC
Mark Horowitz
2014 J jnl
A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sabrina Liao, Mark Horowitz
2014 J jnl
Darkroom: compiling high-level image processing code into hardware pipelines.
ACM Trans. Graph.
James Hegarty, John S. Brunhaver, Zachary DeVito, Jonathan Ragan-Kelley, Noy Cohen, Steven Bell, Artem Vasilyev, Mark Horowitz, Pat Hanrahan
2013 — conf
A Verilog piecewise-linear analog behavior model for mixed-signal validation.
CICC
Sabrina Liao, Mark Horowitz
2013 C conf
An area-efficient minimum-time FFT schedule using single-ported memory.
VLSI-SoC
Stephen Richardson, Ofer Shacham, Dejan Markovic, Mark Horowitz
2013 — conf
Design principles for packet parsers.
ANCS
Glen Gibb, George Varghese, Mark Horowitz, Nick McKeown
2013 C conf
FPU Generator for Design Space Exploration.
IEEE Symposium on Computer Arithmetic
Sameh Galal, Ofer Shacham, John S. Brunhaver, Jing Pu, Artem Vassiliev, Mark Horowitz
2013 A* conf
Forwarding metamorphosis: fast programmable match-action processing in hardware for SDN.
SIGCOMM
Pat Bosshart, Glen Gibb, Hun-Seok Kim, George Varghese, Nick McKeown, Martin Izzard, Fernando A. Mujica, Mark Horowitz
2012 — conf
A 3-stage Pseudo Single-phase Flip-flop family.
VLSIC
Hamid Partovi, Alfred Yeung, Luca Ravezzi, Mark Horowitz
2012 A* conf
Avoiding game over: bringing design to the next level.
DAC
Ofer Shacham, Sameh Galal, Sabarish Sankaranarayanan, Megan Wachs, John S. Brunhaver, Artem Vassiliev, Mark Horowitz, Andrew Danowitz, Wajahat Qadeer, Stephen Richardson
2012 J jnl
Bringing up a chip on the cheap.
IEEE Des. Test
Megan Wachs, Ofer Shacham, Zain Asgar, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
2012 J jnl
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography.
IEEE J. Solid State Circuits
Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz
2012 J jnl
CPU DB: Recording Microprocessor History.
ACM Queue
Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz
2012 J jnl
CPU DB: recording microprocessor history.
Commun. ACM
Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz
2012 — conf
Design Automation Framework for Application-Specific Logic-in-Memory Blocks.
ASAP
Qiuling Zhu, Kaushik Vaidyanathan, Ofer Shacham, Mark Horowitz, Larry T. Pileggi, Franz Franchetti
2012 A* conf
Removing overhead from high-level interfaces.
DAC
Kyle Kelley, Megan Wachs, John P. Stevenson, Stephen Richardson, Mark Horowitz
2012 A* conf
Rethinking DRAM Power Modes for Energy Proportionality.
MICRO
Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo, Benjamin C. Lee, Mark Horowitz
2012 A conf
Sparse matrix-vector multiply on the HICAMP architecture.
ICS
John P. Stevenson, Amin Firoozshahian, Alex Solomatnikov, Mark Horowitz, David R. Cheriton
2012 J jnl
The Frankencamera: an experimental platform for computational photography.
Commun. ACM
Andrew Adams, David E. Jacobs, Jennifer Dolson, Marius Tico, Kari Pulli, Eino-Ville Talvala, Boris Ajdin, Daniel A. Vaquero, Hendrik P. A. Lensch, Mark Horowitz, Sung Hee Park, Natasha Gelfand, Jongmin Baek, Wojciech Matusik, Marc Levoy
2012 A* conf
Towards energy-proportional datacenter memory with mobile DRAM.
ISCA
Krishna T. Malladi, Frank A. Nothaft, Karthika Periyathambi, Benjamin C. Lee, Christos Kozyrakis, Mark Horowitz
2011 — conf
Beyond the horizon: The next 10x reduction in power - Challenges and solutions.
ISSCC
Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul
2011 J jnl
Energy-Efficient Floating-Point Unit Design.
IEEE Trans. Computers
Sameh Galal, Mark Horowitz
2011 A* conf
Global convergence analysis of mixed-signal systems.
DAC
Sangho Youn, Jaeha Kim, Mark Horowitz
2011 A conf
Intermediate representations for controllers in chip generators.
DATE
Kyle Kelley, Megan Wachs, Andrew Danowitz, P. Stevenson, Stephen Richardson, Mark Horowitz
2011 A* conf
Joint DAC/IWBDA special session design and synthesis of biological circuits.
DAC
Douglas Densmore, Mark Horowitz, Smita Krishnaswamy, Xiling Shen, Adam P. Arkin, Erik Winfree, Chris Voigt
2011 C conf
Latency Sensitive FMA Design.
IEEE Symposium on Computer Arithmetic
Sameh Galal, Mark Horowitz
2011 J jnl
Understanding sources of ineffciency in general-purpose chips.
Commun. ACM
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz
2010 A conf
An integrated framework for joint design space exploration of microarchitecture and circuits.
DATE
Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz
2010 A* conf
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.
ISCA
Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz
2010 A* conf
Fortifying analog models with equivalence checking and coverage analysis.
DAC
Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao
2010 A conf
Intent-leveraged optimization of analog circuits via homotopy.
DATE
Metha Jeeradit, Jaeha Kim, Mark Horowitz
2010 J jnl
Rethinking Digital Design: Why Design Must Change.
IEEE Micro
Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz
2010 J jnl
The Frankencamera: an experimental platform for computational photography.
ACM Trans. Graph.
Andrew Adams, David E. Jacobs, Jennifer Dolson, Marius Tico, Kari Pulli, Eino-Ville Talvala, Boris Ajdin, Daniel A. Vaquero, Hendrik P. A. Lensch, Mark Horowitz, Sung Hee Park, Natasha Gelfand, Jongmin Baek, Wojciech Matusik, Marc Levoy
2010 A* conf
Understanding sources of inefficiency in general-purpose chips.
ISCA
Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz
2010 A conf
Why design must change: Rethinking digital design.
DATE
Mark Horowitz
2009 A* conf
A memory system design framework: creating smart memories.
ISCA
Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz
2009 J jnl
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design.
SIGARCH Comput. Archit. News
Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz
2009 J jnl
Energy-Performance Tunable Logic.
IEEE J. Solid State Circuits
Bita Nezamfar, Elad Alon, Mark Horowitz
2009 — conf
Energy-performance tunable logic.
CICC
Bita Nezamfar, Mark Horowitz
2009 B conf
In field, energy-performance tunable FPGA architectures.
FPL
Bita Nezamfar, Mark Horowitz
2009 J jnl
Towards an explanatory and computational theory of scientific discovery
CoRR
Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald A. Pellegrino
2009 J jnl
Towards an explanatory and computational theory of scientific discovery.
J. Informetrics
Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald A. Pellegrino
2009 A* conf
Using a configurable processor generator for computer architecture prototyping.
MICRO
Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz
2009 A* conf
Why design must change: rethinking digital design.
MICRO
Mark Horowitz
2008 J jnl
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.
IEEE J. Solid State Circuits
Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz
2008 J jnl
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects.
IEEE J. Solid State Circuits
Samuel Palermo, Azita Emami-Neyestanak, Mark Horowitz
2008 — conf
A high-speed, low-power 3D-SRAM architecture.
CICC
H. Henry Nho, Mark Horowitz, S. Simon Wong
2008 J jnl
Comparative evaluation of memory models for chip multiprocessors.
ACM Trans. Archit. Code Optim.
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
2008 J jnl
Digital Circuit Design Trends.
IEEE J. Solid State Circuits
Mark Horowitz, Donald Stark, Elad Alon
2008 J jnl
Integrated Regulation for Energy-Efficient Digital Circuits.
IEEE J. Solid State Circuits
Elad Alon, Mark Horowitz
2008 B conf
Processor Performance Modeling using Symbolic Simulation.
ISPASS
Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang, Mark Horowitz
2008 — conf
The case for simple, visible cache coherency.
MSPC
Robert Kunz, Mark Horowitz
2008 A* conf
Verification of chip multiprocessor memory systems using a relaxed scoreboard.
MICRO
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz
2007 J jnl
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS.
IEEE J. Solid State Circuits
John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz
2007 — conf
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications.
ISSCC
Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari
2007 — conf
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects.
ISSCC
Samuel Palermo, Azita Emami-Neyestanak, Mark Horowitz
2007 A* conf
Chip Multi-Processor Generator.
DAC
Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
2007 A* conf
Comparing memory systems for chip multiprocessors.
ISCA
Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis
2007 — conf
Integrated Regulation for Energy-Efficient Digital Circuits.
CICC
Elad Alon, Mark Horowitz
2007 C conf
Robust Energy-Efficient Adder Topologies.
IEEE Symposium on Computer Arithmetic
Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman
2007 Misc conf
Scaling, Power and the Future of CMOS.
VLSI Design
Mark Horowitz
2007 J jnl
Veiling glare in high dynamic range imaging.
ACM Trans. Graph.
Eino-Ville Talvala, Andrew Adams, Mark Horowitz, Marc Levoy
2006 — conf
Improving CDR Performance via Estimation.
ISSCC
Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz
2006 J jnl
Light field microscopy.
ACM Trans. Graph.
Marc Levoy, Ren Ng, Andrew Adams, Matthew Footer, Mark Horowitz
2006 J jnl
Replica compensated linear regulators for supply-regulated phase-locked loops.
IEEE J. Solid State Circuits
Elad Alon, Jaeha Kim, Sudhakar Pamarti, Ken Chang, Mark Horowitz
2006 J jnl
The implementation of a 2-core, multi-threaded itanium family processor.
IEEE J. Solid State Circuits
Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz
2005 — conf
A New Method for Design of Robust Digital Circuits.
ISQED
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd
2005 J jnl
Digital Circuit Optimization via Geometric Programming.
Oper. Res.
Stephen P. Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz
2005 J jnl
Dual photography.
ACM Trans. Graph.
Pradeep Sen, Billy Chen, Gaurav Garg, Stephen R. Marschner, Mark Horowitz, Marc Levoy, Hendrik P. A. Lensch
2005 J jnl
False coupling exploration in timing analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ken Tseng, Mark Horowitz
2005 J jnl
High performance imaging using large camera arrays.
ACM Trans. Graph.
Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Eino-Ville Talvala, Emilio R. Antúnez, Adam Barth, Andrew Adams, Mark Horowitz, Marc Levoy
2005 J jnl
On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures.
Parallel Comput.
Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz
2005 — conf
Scalable circuits for supply noise measurement.
ESSCIRC
Valentin A. Abramzon, Elad Alon, Bita Nezamfar, Mark Horowitz
2005 — conf
Synthetic Aperture Focusing using a Shear-Warp Factorization of the Viewing Transform.
CVPR Workshops
Vaibhav Vaish, Gaurav Garg, Eino-Ville Talvala, Emilio R. Antúnez, Bennett Wilburn, Mark Horowitz, Marc Levoy
2004 B conf
Equalization of modal dispersion in multimode fiber using spatial light modulators.
GLOBECOM
Elad Alon, Vladimir Stojanovic, Joseph M. Kahn, Stephen P. Boyd, Mark Horowitz
2004 — conf
High-Speed Videography Using a Dense Camera Array.
CVPR (2)
Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Marc Levoy, Mark Horowitz
2004 J jnl
Synthetic aperture confocal imaging.
ACM Trans. Graph.
Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas
2004 — conf
The Stream Virtual Machine.
IEEE PACT
Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz
2003 J jnl
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.
IEEE J. Solid State Circuits
Kun-Yung Ken Chang, Jason Wei, Charlie Huang, Simon Li, Kevin S. Donnelly, Mark Horowitz, Yingxuan Li, Stefanos Sidiropoulos
2003 A conf
A Framework for Designing Reusable Analog Circuits.
ICCAD
Dean Liu, Stefanos Sidiropoulos, Mark Horowitz
2003 A* conf
Design of a 10GHz clock distribution network using coupled standing-wave oscillators.
DAC
Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong
2003 C conf
High-Speed Link Design, Then and Now.
ICCD
Mark Horowitz
2003 A* conf
Implementing an untrusted operating system on trusted hardware.
SOSP
David Lie, Chandramohan A. Thekkath, Mark Horowitz
2003 — conf
Modeling and analysis of high-speed links.
CICC
Vladimir Stojanovic, Mark Horowitz
2003 A* conf
Reshaping EDA for power.
DAC
Jan M. Rabaey, Dennis Sylvester, David T. Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang
2003 A* conf
Scaling internet routers using optics.
SIGCOMM
Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David A. B. Miller, Mark Horowitz, Olav Solgaard, Nick McKeown
2003 — conf
Specifying and Verifying Hardware for Tamper-Resistant Software.
S&P
David Lie, John C. Mitchell, Chandramohan A. Thekkath, Mark Horowitz
2002 A conf
Methods for true power minimization.
ICCAD
Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
2001 B conf
Optimizing iterative decoding of low-density parity check codes on programmable pipelined parallel architectures.
GLOBECOM
Ghazi Al-Rawi, John M. Cioffi, Rajeev Motwani, Mark Horowitz
2001 — conf
Optimizing the Mapping of Low-Density Parity Check Codes on Parallel Decoding Architectures.
ITCC
Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz
2001 — conf
Sampling-rate optimization of an interleaved-sampling front-end.
ISCAS (2)
Henrik O. Johansson, Mark Horowitz
2001 A* conf
Using Texture Mapping with Mipmapping to Render a VLSI Layout.
DAC
Jeff Solomon, Mark Horowitz
2000 — conf
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.
Intelligent Memory Systems
Junji Ogawa, Mark Horowitz
2000 A* conf
Architectural Support for Copy and Tamper Resistant Software.
ASPLOS
David Lie, Chandramohan A. Thekkath, Mark Mitchell, Patrick Lincoln, Dan Boneh, John C. Mitchell, Mark Horowitz
2000 A* conf
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).
DAC
Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow
2000 A* conf
Smart Memories: a modular reconfigurable architecture.
ISCA
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
1999 J jnl
A fully digital, energy-efficient, adaptive power-supply regulator.
IEEE J. Solid State Circuits
Gu-Yeon Wei, Mark Horowitz
1999 A conf
Improving coverage analysis and test generation for large designs.
ICCAD
Jules P. Bergmann, Mark Horowitz
1999 A conf
Interconnect scaling implications for CAD.
ICCAD
Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
1999 J jnl
Timing analysis including clock skew.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
David L. Harris, Mark Horowitz, Dean Liu
1999 A* conf
Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology.
DAC
Hema Kapadia, Mark Horowitz
1999 A* conf
Vex - A CAD Toolbox.
DAC
Jules P. Bergmann, Mark Horowitz
1998 — conf
An Evaluation of Directory Schemes for Cache Coherence.
25 Years ISCA: Retrospectives and Reprints
Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
1998 A* conf
Approximate Reachability with BDDs Using Overlapping Projections.
DAC
Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz
1998 J jnl
High-speed electrical signaling: overview and limitations.
IEEE Micro
Mark Horowitz, Chih-Kong Ken Yang, Stefanos Sidiropoulos
1998 J jnl
Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications.
ACM Trans. Comput. Syst.
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
1998 — conf
The Stanford FLASH Multiprocessor.
25 Years ISCA: Retrospectives and Reprints
Jeffrey Kuskin, David Ofelt, Mark A. Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
1998 J jnl
The Tiny Tera: A Packet Switch Core
CoRR
Nick McKeown, Martin Izzard, Adisak Mekkittikul, Bill Ellersick, Mark Horowitz
1997 J jnl
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers.
IEEE J. Solid State Circuits
Stefanos Sidiropoulos, Mark Horowitz
1997 A* conf
Hardware Fault Containment in Scalable Shared-Memory Multiprocessors.
ISCA
Dan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz
1997 C conf
SRT Division Architectures and Implementations.
IEEE Symposium on Computer Arithmetic
David L. Harris, Stuart F. Oberman, Mark Horowitz
1997 J jnl
Tiny Tera: a packet switch core.
IEEE Micro
Nick McKeown, Martin Izzard, Adisak Mekkittikul, William Ellersick, Mark Horowitz
1996 A conf
A low power switching power supply for self-clocked systems.
ISLPED
Gu-Yeon Wei, Mark Horowitz
1996 J jnl
Energy dissipation in general purpose microprocessors.
IEEE J. Solid State Circuits
Ricardo Gonzalez, Mark Horowitz
1996 A* conf
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors.
ISCA
Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith
1996 A ed.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996
ISLPED
Mark Horowitz, Jan M. Rabaey, Brock Barton, Massoud Pedram
1996 A conf
Validation coverage analysis for complex digital designs.
ICCAD
Richard C. Ho, Mark Horowitz
1995 A* conf
Architecture Validation for Processors.
ISCA
Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill
1995 — conf
Array-of-arrays architecture for parallel floating point multiplication.
ARVLSI
H. Dhanesha, K. Falakshahi, Mark Horowitz
1995 — conf
Clustered voltage scaling technique for low-power design.
ISLPD
Kimiyoshi Usami, Mark Horowitz
1995 J jnl
Regenerative feedback repeaters for programmable interconnections.
IEEE J. Solid State Circuits
Ivo Dobbelaere, Mark Horowitz, Abbas El Gamal
1994 — ch.
Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors.
Multithreaded Computer Architecture
James Laudon, Anoop Gupta, Mark Horowitz
1994 J jnl
Eliminating redundant DC equations for asymptotic waveform evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Russell Kao, Mark Horowitz
1994 A* conf
Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations.
ASPLOS
James Laudon, Anoop Gupta, Mark Horowitz
1994 J jnl
Self-timed logic using Current-Sensing Completion Detection (CSCD).
J. VLSI Signal Process.
Mark E. Dean, David L. Dill, Mark Horowitz
1994 A conf
Techniques for Characterizing DRAMs With a 500-MHz Interface.
ITC
James A. Gasbarro, Mark Horowitz
1994 A* conf
The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor.
ASPLOS
Mark A. Heinrich, Jeffrey Kuskin, David Ofelt, John Heinlein, Joel Baxter, Jaswinder Pal Singh, Richard Simoni, Kourosh Gharachorloo, David Nakahira, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
1994 A* conf
The Stanford FLASH Multiprocessor.
ISCA
Jeffrey Kuskin, David Ofelt, Mark A. Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy
1994 J jnl
Timing analysis for piecewise linear Rsim.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Russell Kao, Mark Horowitz
1993 J jnl
A 500-megabyte/s data-rate 4.5 M DRAM.
IEEE J. Solid State Circuits
Natsuki Kushiyama, Shigeo Ohshima, Don Stark, Hiroyuki Noji, Kiyofumi Sakurai, Satoru Takase, Torhu Furuyama, Richard M. Barth, Andy Chan, John Dillon, James A. Gasbarro, Matthew M. Griffin, Mark Horowitz, Thomas H. Lee, Victor Lee
1993 A conf
Piecewise linear models for Rsim.
ICCAD
Russell Kao, Mark Horowitz
1993 J jnl
The design of a high-performance cache controller: a case study in asynchronous synthesis.
Integr.
Steven M. Nowick, Mark E. Dean, David L. Dill, Mark Horowitz
1992 A* conf
Architectural and implementation tradeoffs in the design of multiple-context processors.
ISCA
James Laudon, Anoop Gupta, Mark Horowitz
1992 A* conf
Efficient Superscalar Performance Through Boosting.
ASPLOS
Michael D. Smith, Mark Horowitz, Monica S. Lam
1992 J jnl
The Stanford Dash Multiprocessor.
Computer
Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica S. Lam
1991 A* conf
Modeling the Performance of Limited Pointers Directories for Cache Coherence.
ISCA
Richard Simoni, Mark Horowitz
1991 C conf
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD).
ICCD
Mark E. Dean, David L. Dill, Mark Horowitz
1990 J jnl
Bipolar circuit elements providing self-completion-indication.
IEEE J. Solid State Circuits
Ted E. Williams, Mark Horowitz
1990 A* conf
Boosting Beyond Static Scheduling in a Superscalar Processor.
ISCA
Michael D. Smith, Monica S. Lam, Mark Horowitz
1990 — conf
Design of scalable shared-memory multiprocessors: the DASH approach.
Compcon
Daniel Lenoski, Kourosh Gharachorloo, James Laudon, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica Lam
1990 J jnl
Techniques for calculating currents and voltages in VLSI power supply networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Don Stark, Mark Horowitz
1989 J jnl
An Analytical Cache Model.
ACM Trans. Comput. Syst.
Anant Agarwal, Mark Horowitz, John L. Hennessy
1989 A* conf
Characteristics of Performance-Optimal Multi-Level Cache Hierarchies.
ISCA
Steven A. Przybylski, Mark Horowitz, John L. Hennessy
1989 A* conf
IRSIM: An Incremental MOS Switch-Level Simulator.
DAC
A. Salz, Mark Horowitz
1989 A* conf
Limits on Multiple Instruction Issue.
ASPLOS
Michael D. Smith, Mike Johnson, Mark Horowitz
1988 A* conf
An Evaluation of Directory Schemes for Cache Coherence.
ISCA
Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz
1988 A* conf
Analyzing CMOS Power Supply Networks Using Ariel.
DAC
Don Stark, Mark Horowitz
1988 A conf
Bisim: a simulator for custom ECL circuits.
ICCAD
Russell Kao, Bob Alverson, Mark Horowitz, Don Stark
1988 J jnl
Cache Performance of Operating System and Multiprogramming Workloads.
ACM Trans. Comput. Syst.
Anant Agarwal, John L. Hennessy, Mark Horowitz
1988 A* conf
Performance Tradeoffs in Cache Design.
ISCA
Steven A. Przybylski, Mark Horowitz, John L. Hennessy
1987 A* conf
Architectural Tradeoffs in the Design of MIPS-X.
ISCA
Paul Chow, Mark Horowitz
1987 J jnl
Charge-Sharing Models for Switch-Level Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chorng-Yeong Chu, Mark Horowitz
1987 A* conf
Generating Incremental VLSI Compaction Spacing Constraints.
DAC
Clyde W. Carpenter, Mark Horowitz
1987 A* conf
RED: Resistance Extraction for Digital Simulation.
DAC
Don Stark, Mark Horowitz
1986 A* conf
ATUM: A New Technique for Capturing Address Traces Using Microcode.
ISCA
Anant Agarwal, Richard L. Sites, Mark Horowitz
1983 J jnl
Resistance Extraction from Mask Layout Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark Horowitz, Robert W. Dutton