Mark C. Johnson

16 papers A* 1C 2Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2021 — conf
Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner.
DRC
Xinkang Chen, Chun-Li Lo, Mark C. Johnson, Zhihong Chen, Sumeet Kumar Gupta
2019 — conf
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration.
ACM Great Lakes Symposium on VLSI
Jacob Covey, Mark C. Johnson
2017 — conf
Indiana bicentennial torch project: Trial by fire.
MSE
Todd Wild, Noah Chesnut, Gabriel Martini, Mark C. Johnson
2016 — conf
Student use and assessment of System on Chip (SOC) prototyping resource.
EWME
Matthew Leiter, Lucas Goedde, Emily Fredette, Noah Chesnut, Matthew A. Swabey, Mark C. Johnson
2015 — conf
Satisfying ABET criterion using an industrial Microelectronic Skills Incubator.
MSE
Matthew A. Swabey, Mark C. Johnson
2011 — conf
Interactive application for learning RTL code structures.
MSE
Mark C. Johnson
2009 — conf
Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designs.
MSE
Mark C. Johnson, Eric P. Villasenor, Olga Krachina, Mithuna Thottethodi
2004 — conf
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.
ISQED
Dongku Kang, Mark C. Johnson, Kaushik Roy
2003 C conf
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.
ICCD
Dongku Kang, Mark C. Johnson, Kaushik Roy
2002 J jnl
Leakage control with efficient use of transistor stacks in single threshold CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
2001 — conf
igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool Access.
MSE
Mark C. Johnson
1999 J jnl
Design and optimization of dual-threshold circuits for low-voltage low-power applications.
IEEE Trans. Very Large Scale Integr. Syst.
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
1999 A* conf
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS.
DAC
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1999 J jnl
Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
1997 J jnl
Datapath scheduling with multiple supply voltages and level converters.
ACM Trans. Design Autom. Electr. Syst.
Mark C. Johnson, Kaushik Roy
1996 C conf
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints.
ICCD
Mark C. Johnson, Kaushik Roy