Mark A. Indovina

17 papers C 2Journal 5Unranked 10
YearRankTypeTitle / Venue / Authors
2025 — conf
BrIM: A Branching In-Memory Accelerator.
ACM Great Lakes Symposium on VLSI
Stefan Maczynski, Amlan Ganguly, Mark A. Indovina, Purab Ranjan Sutradhar, Sai Manoj Pudukotai Dinakarrao, Sathwika Bavikadi
2025 — conf
The State of Simulation Frameworks for Evaluating Emerging LLM Accelerators.
ACM Great Lakes Symposium on VLSI
Stefan Maczynski, Amlan Ganguly, Mark A. Indovina
2024 J jnl
3DL-PIM: A Look-Up Table Oriented Programmable Processing in Memory Architecture Based on the 3-D Stacked Memory for Data-Intensive Applications.
IEEE Trans. Emerg. Top. Comput.
Purab Ranjan Sutradhar, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly
2024 J jnl
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark A. Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao
2023 — conf
CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs.
SOCC
Christie Agbalessi, Mark A. Indovina
2023 — conf
FlutPIM: : A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications.
ACM Great Lakes Symposium on VLSI
Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark A. Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
2022 — conf
Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware.
SOCC
Prangon Das, Purab Ranjan Sutradhar, Mark A. Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
2022 J jnl
Look-up-Table Based Processing-in-Memory Architecture With Programmable Precision-Scaling for Deep Learning Applications.
IEEE Trans. Parallel Distributed Syst.
Purab Ranjan Sutradhar, Sathwika Bavikadi, Mark Connolly, Savankumar Prajapati, Mark A. Indovina, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly
2022 C conf
POLAR: Performance-aware On-device Learning Capable Programmable Processing-in-Memory Architecture for Low-Power ML Applications.
DSD
Sathwika Bavikadi, Purab Ranjan Sutradhar, Mark A. Indovina, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao
2021 C conf
Flexible Instruction Set Architecture for Programmable Look-up Table based Processing-in-Memory.
ICCD
Mark Connolly, Purab Ranjan Sutradhar, Mark A. Indovina, Amlan Ganguly
2020 — conf
The IANET Hardware Accelerator for Audio and Visual Data Classification.
SoCC
Rohini J. Gillela, Amlan Ganguly, Dorin Patru, Mark A. Indovina
2020 J jnl
pPIM: A Programmable Processor-in-Memory Architecture With Precision-Scaling for Deep Learning.
IEEE Comput. Archit. Lett.
Purab Ranjan Sutradhar, Mark Connolly, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao, Mark A. Indovina, Amlan Ganguly
2018 — conf
A 0.24pJ/bit, 16Gbps OOK Transmitter Circuit in 45-nm CMOS for Inter and Intra-Chip Wireless Interconnects.
ACM Great Lakes Symposium on VLSI
Tanmay Shinde, Suryanarayanan Subramaniam, Padmanabh Deshmukh, M. Meraj Ahmed, Mark A. Indovina, Amlan Ganguly
2018 — conf
Testing WiNoC-Enabled Multicore Chips with BIST for Wireless Interconnects.
NOCS
Abhishek Vashist, Amlan Ganguly, Mark A. Indovina
2017 — conf
A 0.36pJ/bit, 17Gbps OOK receiver in 45-nm CMOS for inter and intra-chip wireless interconnects.
SoCC
Suryanarayanan Subramaniam, Tanmay Shinde, Padmanabh Deshmukh, Md Shahriar Shamim, Mark A. Indovina, Amlan Ganguly
2006 — conf
Industrially proving the SPIRIT consortium specifications for design chain integration.
DATE Designers' Forum
Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark A. Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud
2004 J jnl
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications.
J. Circuits Syst. Comput.
Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark A. Indovina