Marius Strum - RankMe

50 papers B 2C 1Misc 2Journal 10Unranked 35

Year	Rank	Type	Title / Venue / Authors
2015	J	`jnl`	A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models. J. Electron. Test. Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2015	J	`jnl`	NoC-Based Protection for SoC Time-Driven Attacks. IEEE Embed. Syst. Lett. Martha Johanna Sepúlveda, Jean-Philippe Diguet, Marius Strum, Guy Gogniat
2015	—	`conf`	TSV protection: Towards secure 3D-MPSoC. LASCAS Martha Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Ricardo Pires, Marius Strum
2015	—	`conf`	Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS. LATS Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang
2015	J	`jnl`	Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems. Int. J. Reconfigurable Comput. Jonas Gomes Filho, Marius Strum, Jiang Chau Wang
2014	—	`conf`	3D-LeukoNoC: A dynamic NoC protection. ReConFig Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, César Pedraza, Marius Strum
2014	—	`conf`	A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs. LATW Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2014	—	`conf`	Elastic security zones for NoC-based 3D-MPSoCs. ICECS Johanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Cesar A. Zeferino, Marius Strum
2013	—	`conf`	3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping. GECCO (Companion) Martha Johanna Sepúlveda, Guy Gogniat, Daniel Mauricio Sepúlveda, Ricardo Pires, Jiang Chau Wang, Marius Strum
2013	—	`conf`	A strategy for mapping reconfigurable cores in NoCs. LASCAS Jonas Gomes Filho, Marius Strum, Wang Jiang Chau
2013	—	`conf`	An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2013	—	`conf`	Formal equivalence checking between high-level and RTL hardware designs. LATW Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2013	—	`conf`	Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions. IDT Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2013	—	`conf`	Long range dependence in intrachip transaction level traffic. LASCAS Jorge González, Gustavo A. Patiño-Álvarez, Marius Strum, Wang Jiang Chau
2013	J	`jnl`	Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification. J. Electron. Test. Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
2013	—	`conf`	PrOCov: Probabilistic output coverage model. LATW Joel Ivan Munoz Quispe, Marius Strum, Jiang Chau Wang
2013	—	`conf`	QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs. LASCAS Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, César Pedraza, Wang Jiang Chau, Marius Strum
2013	Misc	`conf`	Scalable NoC-based architecture of neural coding for new efficient associative memories. CODES+ISSS Jean-Philippe Diguet, Marius Strum, Nicolas Le Griguer, Lydie Caetano, Martha Johanna Sepúlveda
2013	—	`conf`	Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Hybrid-on-chip communication architecture for dynamic MP-SoC protection. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping. GECCO (Companion) Martha Johanna Sepúlveda, Jiang Chau Wang, Marius Strum, César Pedraza, Guy Gogniat, Ricardo Pires
2012	J	`jnl`	QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection. Int. J. Reconfigurable Comput. Johanna Sepúlveda, Ricardo Pires, Guy Gogniat, Jiang Chau Wang, Marius Strum
2012	—	`conf`	Workload and task characterization based on operation modes timing analysis. SoCC Gustavo A. Patiño-Álvarez, Jorge González, Jiang Chau Wang, Marius Strum
2011	J	`jnl`	A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling. J. Electron. Test. Carlos Ivan Castro Marquez, Edgar Leonardo Romero Tobar, Marius Strum, Jiang Chau Wang
2011	—	`conf`	Dynamic NoC-based architecture for MPSoC security implementation. SBCCI Johanna Sepúlveda, Guy Gogniat, Ricardo Pires, Jiang Chau Wang, Marius Strum
2011	—	`conf`	Formally verifying an RTOS scheduling monitor IP core in embedded systems. LATW Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau, Fabian Vargas
2010	—	`conf`	Automatic generation of a parameter-domain-based functional input coverage model. LATW Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau
2010	J	`jnl`	Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection. Trans. Comput. Sci. Johanna Sepúlveda, Ricardo Pires, Marius Strum, Jiang Chau Wang
2010	—	`conf`	The LRD traffic impact on the NoC-based SoCs. SBCCI Johanna Sepúlveda, Marius Strum, Jiang Chau Wang, Ricardo Pires
2009	—	`conf`	A PD-based methodology to enhance efficiency in testbenches with random stimulation. SBCCI Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang
2009	B	`conf`	The Multiple Pairs SMO: A modified SMO algorithm for the acceleration of the SVM training. IJCNN Raul Acosta Hernandez, Marius Strum, Jiang Chau Wang, Jose Artur Quilici González
2008	J	`jnl`	Burst-Mode Asynchronous Controllers on FPGA. Int. J. Reconfigurable Comput. Duarte Lopes de Oliveira, Marius Strum, Sandro S. Sato
2007	—	`conf`	A System-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modeling. ISVLSI Frederico De Faria, Marius Strum, Jiang Chau Wang
2005	B	`conf`	A Dynamically Reconfigurable Bluetooth Base Band Unit. FPL John Esquiagola, Guilherme Ozari, Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
2005	Misc	`conf`	Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor. CODES+ISSS Edgar Leonardo Romero, Marius Strum, Jiang Chau Wang
2005	—	`conf`	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
2004	J	`jnl`	Datapath BIST Insertion Using Pre-Characterized Area and Testability Data. J. Electron. Test. Jiang Chau Wang, Paulo Sérgio Cardoso, Jose Artur Quilici González, Marius Strum, Ricardo Pires
2003	C	`conf`	Exploring Models of Computation through Static Analysis. FDL Ivan Jeukens, Marius Strum
2003	J	`jnl`	Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang, Wagner Chiepa Cunha
2002	—	`conf`	A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications. LATW Wang Jiang Chau, Paulo Sérgio Cardoso, Marius Strum, Ricardo Pires
2002	—	`conf`	BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units. LATW Wang Jiang Chau, Jose Artur Quilici González, Marius Strum, Ricardo Pires
2002	—	`conf`	Power Management Exploration for a Block Turbo Decoder. SBCCI João Martins, Marius Strum
2001	—	`conf`	Synthesis of Multi-Burst Controllers as Modified Huffman Machines. SBCCI Duarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau
2000	—	`conf`	On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs. SBCCI Ivan Jeukens, Marius Strum
2000	—	`conf`	Self Test Built-in Plan for Data-Path Functional Units. LATW Jose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau
2000	—	`conf`	Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. SBCCI Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha
1999	—	`conf`	Architectural Transformations for Hierarchical Algorithmic Descriptions. VLSI Marcio Yukio Teruya, Marius Strum, Jiang Chau Wang
1999	—	`conf`	SINMEF - A Decomposition Based Synthesis Tool for Large FSMs. Great Lakes Symposium on VLSI Carlos Humberto Llanos Quintero, Marius Strum
1998	—	`conf`	A Methodology for Minimum Area Cellular Automata Generation. Asian Test Symposium Paulo Sérgio Cardoso, Marius Strum, José Roberto de A. Amazonas, Jiang Chau Wang
1998	—	`conf`	Exploring Concurrency in Data Path Functional Units BIST Plan Optimization: A Study-Case. SBCCI José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau