Marius Evers

12 papers A* 5Journal 4Unranked 2
YearRankTypeTitle / Venue / Authors
2007 — conf
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.
ISPD
Jeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari
2001 J jnl
Understanding branches and designing branch predictors for high-performance microprocessors.
Proc. IEEE
Marius Evers, Tse-Yu Yeh
2000 — —
Improving branch prediction by understanding branch behavior.
Marius Evers
1998 A* conf
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.
ISCA
Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt
1998 A* conf
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.
ISCA
Sanjay J. Patel, Marius Evers, Yale N. Patt
1998 J jnl
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.
Int. J. Parallel Program.
Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
1998 A* conf
Variable Length Path Branch Prediction.
ASPLOS
Jared Stark, Marius Evers, Yale N. Patt
1997 J jnl
Improving branch prediction accuracy by reducing pattern history table interference.
Int. J. Parallel Program.
Po-Yung Chang, Marius Evers, Yale N. Patt
1997 J jnl
One Billion Transistors, One Uniprocessor, One Chip.
Computer
Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark
1996 — conf
Improving branch prediction accuracy by reducing pattern history table interference.
IEEE PACT
Po-Yung Chang, Marius Evers, Yale N. Patt
1996 A* conf
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures.
MICRO
Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt
1996 A* conf
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.
ISCA
Marius Evers, Po-Yung Chang, Yale N. Patt