Marisa López-Vallejo

77 papers B 1C 9Journal 28Unranked 36
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Javier De Mena Pacheco, Juan M. Carrillo, Tomás Palacios, Marisa López-Vallejo
2025 J jnl
An Ultra-Low-Power Flip-Flop With Near-Threshold Robust Operation and Redundant-Free Internal Clock Transitions.
IEEE Trans. Circuits Syst. I Regul. Pap.
Borja Gutiérrez De Cabiedes, Javier De Mena Pacheco, Amadeo de Gracia Herranz, Marisa López-Vallejo
2025 J jnl
Design and Implementation of a Real-Time Low-Latency Automatic Modulation Classifier.
IEEE Trans. Instrum. Meas.
Samuel López Asunción, Jorge Gonzalez-Lopez, Carlos Garcia de la Cueva, Marisa López-Vallejo, Jesús Grajal
2025 — conf
Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications.
DFT
Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic
2025 — conf
Ultra-Narrow Current Pulses Measurement Using a Cost-Effective Instrumentation System.
DCIS
Amadeo de Gracia Herranz, Borja Gutiérrez De Cabiedes, Javier De Mena Pacheco, Marisa López-Vallejo
2025 J jnl
Uniformly Distributed CORDIC.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mario Garrido, Daniel Medina, Pedro Paz, Marisa López-Vallejo
2024 — conf
A Lightweight Analog RFID Front-End for Interfacing Sensors.
DCIS
Javier De Mena Pacheco, Borja Gutiérrez De Cabiedes, Amadeo de Gracia Herranz, Marisa López-Vallejo
2024 — conf
Drift Compensation in Multilevel PCM for in-Memory Computing Accelerators.
IRPS
L. Pistolesi, Artem Glukhov, Amadeo de Gracia Herranz, Marisa López-Vallejo, Marcella Carissimi, Marco Pasotti, Pier Luigi Rolandi, Andrea Redaelli, I. Muñoz-Martín, S. Bianchi, Andrea Bonfanti, Daniele Ielmini
2024 — conf
Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction.
NorCAS
Oliver Schrape, Anselm Breitenreiter, Li Lu, Marko S. Andjelkovic, Ernesto Pun-Garcia, Marisa López-Vallejo, Milos Krstic
2023 — conf
Ring Oscillator Circuits in Flexible aIGZO Technology for Biosignal Acquisition.
DCIS
Alba Páez-Montoro, Javier De Mena Pacheco, Marisa López-Vallejo, Celia López-Ongil, Susana Patón
2023 J jnl
Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond.
IEEE Trans. Circuits Syst. I Regul. Pap.
Víctor Manuel Bautista, Mario Garrido, Marisa López-Vallejo
2022 — conf
Data Synchronization in Non-Uniform Latency Custom DSP Designs.
DCIS
Samuel López Asunción, Pablo Ituero, Marisa López-Vallejo, Jesús Grajal
2022 J jnl
Power-Efficient Implementation of Ternary Neural Networks in Edge Devices.
IEEE Internet Things J.
Miguel Molina, Javier Mendez, Diego Pedro Morales, Encarnación Castillo, Marisa López-Vallejo, Manuel Pegalajar
2022 J jnl
Reference-free power supply monitor with enhanced robustness against process and temperature variations.
Integr.
Hernan Aparicio, Pablo Ituero, Marisa López-Vallejo
2021 — conf
A 65nm Current and Voltage Reference with Improved Line Regulation for Implantable Biosensors.
DCIS
Javier De Mena Pacheco, Marisa López-Vallejo
2021 J jnl
Time to Digital Sensing for Multilevel RRAM Cells.
IEEE Access
Amadeo de Gracia Herranz, Marisa López-Vallejo
2020 — conf
Algorithm-Architecture Optimization for Linear and Quadratic Regression on Reconfigurable Platforms.
DCIS
Samuel López Asunción, Marisa López-Vallejo, Jesús Grajal
2020 — conf
An ultra-low power deep sub-micron fast start-up circuit with added line regulation.
DCIS
Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio
2020 J jnl
Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations.
Integr.
Amadeo de Gracia Herranz, Marisa López-Vallejo
2019 — conf
A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology.
DCIS
Asghar Bahramali, Marisa López-Vallejo, Carlos A. López-Barrio
2019 J jnl
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage.
Integr.
Asghar Bahramali, Marisa López-Vallejo
2019 — conf
Temperature-aware writing architecture for multilevel memristive cells.
PATMOS
Amadeo de Gracia Herranz, Marisa López-Vallejo
2018 — conf
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications.
PATMOS
Asghar Bahramali, Marisa López-Vallejo
2018 J jnl
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fernando García-Redondo, Marisa López-Vallejo
2018 — conf
Performance-oriented Implementation of Hilbert Filters on FPGAs.
DCIS
Daniel Fortun, Carlos Garcia de la Cueva, Jesús Grajal, Marisa López-Vallejo, Carlos A. López-Barrio
2017 — conf
Advanced integration of variability and degradation in RRAM SPICE compact models.
SMACD
Fernando García-Redondo, Marisa López-Vallejo, Carlos A. López-Barrio
2017 J jnl
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
IEEE Trans. Very Large Scale Integr. Syst.
Fernando García-Redondo, Pablo Royer, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero, Carlos A. López-Barrio
2016 J jnl
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model.
IEEE Trans. Parallel Distributed Syst.
Jose M. Nadal-Serrano, Marisa López-Vallejo
2016 — conf
Reliable design methodology: The combined effect of radiation, variability and temperature.
SMACD
Fernando García-Redondo, Marisa López-Vallejo, Hernan Aparicio, Pablo Ituero
2016 J jnl
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds.
IEEE Trans. Circuits Syst. I Regul. Pap.
Fernando García-Redondo, Robert P. Gowers, Albert Crespo-Yepes, Marisa López-Vallejo, Liudi Jiang
2015 — conf
A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs.
DFTS
Ignacio Herrera-Alzu, Marisa López-Vallejo, C. Gil Soriano
2015 C conf
A thermal adaptive scheme for reliable write operation on RRAM based architectures.
ICCD
Fernando García-Redondo, Marisa López-Vallejo, Pablo Ituero
2015 J jnl
An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle.
IEEE Trans. Circuits Syst. I Regul. Pap.
Javier Agustin, Marisa López-Vallejo
2015 — conf
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.
NANOARCH
Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo
2015 J jnl
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms.
IEEE Trans. Instrum. Meas.
Victor Iglesias, Jesús Grajal, Miguel A. Sánchez Marcos, Marisa López-Vallejo
2015 J jnl
Real-time low-complexity automatic modulation classifier for pulsed radar signals.
IEEE Trans. Aerosp. Electron. Syst.
Victor Iglesias, Jesús Grajal, Pablo Royer, Miguel A. Sánchez Marcos, Marisa López-Vallejo, Omar A. Yeste Ojeda
2014 J jnl
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs).
Sensors
Carlos Gómez Osuna, Pablo Ituero, Marisa López-Vallejo
2013 J jnl
A 0.0016 mm
Sensors
Pablo Ituero, Marisa López-Vallejo, Carlos A. López-Barrio
2013 C conf
A Low-Area Reference-Free Power Supply Sensor.
DSD
Carlos Benito, Pablo Ituero, Marisa López-Vallejo
2013 — conf
A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node.
ACM Great Lakes Symposium on VLSI
Pablo Royer, Marisa López-Vallejo
2013 J jnl
Floating-Point Exponentiation Units for Reconfigurable Computing.
ACM Trans. Reconfigurable Technol. Syst.
Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, Bogdan Pasca
2013 J jnl
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator.
J. Signal Process. Syst.
Pedro Echeverría, Marisa López-Vallejo
2012 — conf
A monitoring infrastructure for FPGA self-awareness and dynamic adaptation.
ICECS
Carlos Gómez Osuna, Miguel A. Sánchez Marcos, Pablo Ituero, Marisa López-Vallejo
2012 C conf
Hardware Reuse Improvement through the Domain Specific Language dHDL.
ISPA
Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias
2012 B conf
Improving Hardware Reuse through XML-based Interface Encapsulation.
ICECCS
Miguel Angel Sánchez, Marisa López-Vallejo, Carlos Angel Iglesias, Carlos A. López-Barrio
2011 J jnl
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs.
Microprocess. Microsystems
Pedro Echeverría, Marisa López-Vallejo
2011 C conf
On-chip Monitoring: A Light-Weight Interconnection Network Approach.
DSD
Pablo Ituero, Marisa López-Vallejo, Miguel A. Sánchez Marcos, Carlos Gómez Osuna
2011 — conf
Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications.
EUSIPCO
Jesús Grajal, Omar A. Yeste Ojeda, Miguel Angel Sánchez, Mario Garrido, Marisa López-Vallejo
2011 — conf
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs.
PATMOS
Ignacio Herrera-Alzu, Marisa López-Vallejo
2010 J jnl
Thermal analysis and modeling of embedded processors.
Comput. Electr. Eng.
José Luis Ayala, Cándido Méndez, Marisa López-Vallejo
2009 — conf
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs.
ICECS
Pedro Echeverría, Marisa López-Vallejo, Walter Bolognesi, Carlos A. López-Barrio
2009 — ch.
SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.
Embedded Systems Design and Verification
José L. Ayala, Marisa López-Vallejo, Davide Bertozzi, Luca Benini
2008 — conf
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design.
e-Learning
Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo
2008 J jnl
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
Int. J. Embed. Syst.
José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum
2008 — conf
An FPGA run-time parameterisable Log-Normal Random Number Generator.
ARC
Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk
2008 C conf
Designing Highly Parameterized Hardware using xHdl.
FDL
Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo
2008 — conf
Experimental methodology for power characterization of FPGAs.
ICECS
Ignacio Herrera-Alzu, Miguel Angel Sánchez, Marisa López-Vallejo, Pedro Echeverría
2008 J jnl
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integr.
David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
2008 J jnl
Power Considerations in Banked CAMs: A Leakage Reduction Approach.
VLSI Design
Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo
2008 — conf
Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach.
ICECS
Pedro Echeverría, Marisa López-Vallejo, Jose María Pesquero
2007 J jnl
Energy-aware compilation and hardware design for VLIW embedded systems.
Int. J. Embed. Syst.
José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest
2007 — conf
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.
ICESS
Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna
2007 C conf
Leakage-based On-Chip Thermal Sensor for CMOS Technology.
ISCAS
Pablo Ituero, José L. Ayala, Marisa López-Vallejo
2007 C conf
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
ISCAS
Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo
2007 — conf
Thermal Characterization and Thermal Management in Processor-Based Systems.
Power-aware Computing Systems
José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio
2006 — conf
Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors.
ICECS
José Luis Ayala, Cándido Méndez, Marisa López-Vallejo
2006 — conf
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation.
FPT
Miguel A. Sánchez Marcos, Mario Garrido, Marisa López-Vallejo, Carlos A. López-Barrio
2006 — conf
Compiler-Driven Leakage Energy Reduction in Banked Register Files.
PATMOS
David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo
2006 — conf
Leakage Energy Reduction in Banked Content Addressable Memories.
ICECS
Pedro Echeverría, José Luis Ayala, Marisa López-Vallejo
2006 — conf
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.
ASAP
Pablo Ituero, Marisa López-Vallejo
2006 C conf
Target Independent Thermal Modeling for Embedded Processors.
IES
Cándido Méndez, José Luis Ayala, Marisa López-Vallejo
2005 — conf
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems.
Power-aware Computing Systems
José Luis Ayala, Marisa López-Vallejo
2005 J jnl
Integrating functional and power simulation in embedded systems design.
J. Embed. Comput.
José Luis Ayala, Marisa López-Vallejo
2005 — ch.
State-of-the-Art SoC Communication Architectures.
Embedded Systems Handbook
Davide Bertozzi, Luca Benini, Marisa López-Vallejo, José L. Ayala
2004 C conf
Improving IP core reuse through the application of the meta-language xHDL.
FDL
Marcos M. A. Sanchez, Fernandez Herrero, Marisa López-Vallejo
2003 — ch.
State Space Compression in History Driven Quasi-Static Scheduling.
Embedded Software for SoC
Antonio G. Lomeña, Marisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
2002 — conf
Block processing technique for low power turbo decoder design.
VTC Spring
Inkyu Lee, Marisa López-Vallejo, Syed Aon Mujtaba