Marios C. Papaefthymiou

94 papers A* 9A 18B 2C 3Journal 30Unranked 32

Year	Rank	Type	Title / Venue / Authors
2018	—	`conf`	A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. ESSCIRC Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
2018	J	`jnl`	Rethinking Numerical Representations for Deep Neural Networks. CoRR Parker Hill, Babak Zamirai, Shengshuo Lu, Yu-Wei Chao, Michael Laurenzano, Mehrzad Samadi, Marios C. Papaefthymiou, Scott A. Mahlke, Thomas F. Wenisch, Jia Deng, Lingjia Tang, Jason Mars
2017	—	`conf`	20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. ISSCC Hsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou
2017	—	`conf`	A 1.25pJ/bit 0.048mm A-SSCC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2016	—	`conf`	A 5.5GHz 0.84TOPS/mm A-SSCC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2016	J	`jnl`	Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
2015	—	`conf`	1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. VLSIC Shengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou
2015	—	`conf`	A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. A-SSCC Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
2015	—	`conf`	Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. ASP-DAC Seyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim
2014	—	`conf`	27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. ISSCC Tai-Chuan Ou, Zhengya Zhang, Marios C. Papaefthymiou
2013	A*	`conf`	Computational sprinting on a hardware/software testbed. ASPLOS Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
2013	J	`jnl`	Designing for Responsiveness with Computational Sprinting. IEEE Micro Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
2013	J	`jnl`	Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger
2013	J	`jnl`	Utilizing Dark Silicon to Save Energy with Computational Sprinting. IEEE Micro Arun Raghavan, Laurel Emurian, Lei Shao, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
2012	A*	`conf`	Computational sprinting. HPCA Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin
2012	J	`jnl`	Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
2012	—	`conf`	Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger
2011	—	`conf`	A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. ESSCIRC Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou
2010	J	`jnl`	187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
2009	—	`conf`	A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou
2009	—	`conf`	A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou
2008	J	`jnl`	Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
2007	—	`conf`	A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou
2007	J	`jnl`	A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. IEEE Trans. Circuits Syst. II Express Briefs Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz, Marios C. Papaefthymiou
2007	J	`jnl`	Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou
2007	J	`jnl`	RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power CoRR Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
2007	—	`conf`	Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu
2006	—	`conf`	900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou
2006	A	`conf`	Parallelizing post-placement timing optimization. IPDPS Jiyoun Kim, Marios C. Papaefthymiou, José Luis Neves
2006	J	`jnl`	Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
2005	A	`conf`	A GHz-class charge recovery logic. ISLPED Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
2005	—	`conf`	Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler
2005	J	`jnl`	Charge-Recovery Computing on Silicon. IEEE Trans. Computers Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2005	—	`conf`	Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
2005	J	`jnl`	HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xun Liu, Marios C. Papaefthymiou
2005	C	`conf`	Multi-Session Partitioning for Parallel Timing Optimization. PDCAT Jiyoun Kim, José Neves, Marios C. Papaefthymiou
2005	A	`conf`	RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
2005	—	`conf`	Two-Phase Resonant Clock Distribution. ISVLSI Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler
2004	J	`jnl`	A Markov chain sequence generator for power macromodeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xun Liu, Marios C. Papaefthymiou
2004	—	`conf`	A synchronous interface for SoCs with multiple clock domains. SoCC Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky
2004	A	`conf`	An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab
2004	—	`conf`	Clock tree layout design for reduced delay uncertainty. SoCC Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2004	A	`conf`	Constant-load energy recovery memory for efficient high-speed operation. ISLPED Joohee Kim, Marios C. Papaefthymiou
2004	—	`conf`	Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
2004	—	`conf`	Experimental Evaluation of Resonant Clock Distribution. ISVLSI Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou
2004	A*	`conf`	Practical repeater insertion for low power: what repeater library do we need? DAC Xun Liu, Yuantao Peng, Marios C. Papaefthymiou
2003	A	`conf`	A 225 MHz resonant clocked ASIC chip. ISLPED Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou
2003	J	`jnl`	A true single-phase energy-recovery multiplier. IEEE Trans. Very Large Scale Integr. Syst. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2003	J	`jnl`	Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans. Very Large Scale Integr. Syst. Joohee Kim, Marios C. Papaefthymiou
2003	J	`jnl`	Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. Xun Liu, Marios C. Papaefthymiou
2003	—	`conf`	Energy Recovering ASIC Design. ISVLSI Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou
2003	J	`jnl`	Fine-grain real-time reconfigurable pipelining. IBM J. Res. Dev. Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2003	—	`conf`	HyPE: hybrid power estimation for IP-based programmable systems. ASP-DAC Xun Liu, Marios C. Papaefthymiou
2003	A	`conf`	Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
2002	A	`conf`	A Markov chain sequence generator for power macromodeling. ICCAD Xun Liu, Marios C. Papaefthymiou
2002	A*	`conf`	Design of a high-throughput low-power IS95 Viterbi decoder. DAC Xun Liu, Marios C. Papaefthymiou
2002	A	`conf`	Energy recovering static memory. ISLPED Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2002	—	`conf`	Incorporation of input glitches into power macromodeling. ISCAS (4) Xun Liu, Marios C. Papaefthymiou
2002	J	`jnl`	Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
2001	A*	`conf`	A True Single-Phase 8-bit Adiabatic Multiplier. DAC Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2001	—	`conf`	A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
2001	A	`conf`	A resonant clock generator for single-phase adiabatic systems. ISLPED Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou
2001	A	`conf`	A static power estimation methodolodgy for IP-based design. DATE Xun Liu, Marios C. Papaefthymiou
2001	—	`conf`	Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. ARVLSI Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
2001	J	`jnl`	Symbolic debugging of embedded hardware and software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou
2001	J	`jnl`	True single-phase adiabatic circuitry. IEEE Trans. Very Large Scale Integr. Syst. Suhwan Kim, Marios C. Papaefthymiou
2000	—	`conf`	Dynamic Memory Design for Low Data-Retention Power. PATMOS Joohee Kim, Marios C. Papaefthymiou
2000	J	`jnl`	Optimizing computations for effective block-processing. ACM Trans. Design Autom. Electr. Syst. Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
2000	—	`conf`	Symbolic debugging of globally optimized behavioral specifications. ASP-DAC Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou
1999	A	`conf`	Analytical macromodeling for high-level power estimation. ICCAD Giuseppe Bernacchia, Marios C. Papaefthymiou
1999	J	`jnl`	Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. Des. Autom. Embed. Syst. Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou
1999	A*	`conf`	Maximizing Performance by Retiming and Clock Skew Scheduling. DAC Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
1999	A	`conf`	Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
1999	A	`conf`	Single-phase source-coupled adiabatic logic. ISLPED Suhwan Kim, Marios C. Papaefthymiou
1998	A	`conf`	Asymptotically efficient retiming under setup and hold constraints. ICCAD Marios C. Papaefthymiou
1998	A	`conf`	True single-phase energy-recovering logic for low-power, high-speed VLSI. ISLPED Suhwan Kim, Marios C. Papaefthymiou
1997	J	`jnl`	Computing Strictly-Second Shortest Paths. Inf. Process. Lett. Kumar N. Lalgudi, Marios C. Papaefthymiou
1997	J	`jnl`	Optimizing two-phase, level-clocked circuitry. J. ACM Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou
1997	C	`conf`	Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. JSSPP Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante
1997	J	`jnl`	Retiming edge-triggered circuits under general delay models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kumar N. Lalgudi, Marios C. Papaefthymiou
1996	C	`conf`	A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. JSSPP Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante
1996	B	`conf`	An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. SPAA Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
1996	A	`conf`	Fixed-phase retiming for low power design. ISLPED Marios C. Papaefthymiou, Kumar N. Lalgudi
1996	A*	`conf`	Optimizing Systems for Effective Block-Processing: The DAC Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
1996	J	`jnl`	Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. Perform. Evaluation Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou
1995	A*	`conf`	DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. DAC Kumar N. Lalgudi, Marios C. Papaefthymiou
1995	—	`conf`	Efficient retiming under a general delay model. ARVLSI Kumar N. Lalgudi, Marios C. Papaefthymiou
1994	—	`conf`	Implementing parallel shortest-paths algorithms. Parallel Algorithms Marios C. Papaefthymiou, Joseph Rodrigue
1994	—	`conf`	Memory Assignment for Multiprocessor Caches through Grey Coloring. PARLE Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou
1994	A	`conf`	Precomputation-based sequential logic optimization for low power. ICCAD Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1994	J	`jnl`	Precomputation-based sequential logic optimization for low power. IEEE Trans. Very Large Scale Integr. Syst. Mazhar Alidina, José Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
1994	J	`jnl`	Understanding Retiming Through Maximum Avarage-Delay Cycles. Math. Syst. Theory Marios C. Papaefthymiou
1993	A*	`conf`	TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. DAC Marios C. Papaefthymiou, Keith H. Randall
1991	B	`conf`	Understanding Retiming Through Maximum Average-Weight Cycles. SPAA Marios C. Papaefthymiou