Mario R. Casu

81 papers A* 2A 9C 7Journal 36Unranked 27
YearRankTypeTitle / Venue / Authors
2025 J jnl
Accelerating Mixed-Precision QNN Inference on RISC-V MCUs With the STAR-MAC Unit.
IEEE Access
Edward Manca, Luca Urbinati, Mario R. Casu
2025 J jnl
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Roberto Bosio, Filippo Minnella, Teodoro Urso, Mario R. Casu, Luciano Lavagno, Mihai T. Lazarescu, Paolo Pasini
2024 J jnl
High-Level Design of Precision-Scalable DNN Accelerators Based on Sum-Together Multipliers.
IEEE Access
Luca Urbinati, Mario R. Casu
2024 J jnl
Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lorenzo Lagostina, Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno
2024 A conf
STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads.
DATE
Edward Manca, Luca Urbinati, Mario R. Casu
2024 C conf
WIP: Building an Education Ecosystem for Next Generation Microelectronics Experts in Green and Circular Economy with Digitally-Supported Teaching Methods for Sustainable Chips and Applications (EU Project GreenChips-EDU).
FIE
Klaus Hofmann, Ferdinand Keil, David Riehl, Alicja Michalowska-Forsyth, Nikolaus Czepl, Sarah Woywod, Dominik Zupan, Mario R. Casu, Carlo Ricciardi, Massimo Violante, Mariagrazia Graziano, Yuri Ardesi, Fabrizio Mo, Dominik Berger, Sabine Sill, Volker Visotschnig, Panagiota Morfouli, Liliana Prejbeanu, Katell Morin-Allory, Cyrille Chavet, Davide Bucci, Skandar Basrour, Jean-Christophe Crebier, Nhu-Huan Nguyen, Ernesto Quisbert-Trujillo, Christian Defélix, Isabelle Corbett-Etchevers, Johannes Sturm, Jens Peter Konrath, Ulla Birnbacher, Thomas Klinger, Wolfgang Werth, Jorge Fernandes, Marcelino B. Santos, Antonio Rubio, Alba Pagès-Zamora, Josep Pegueroles, Jordi Salazar, Beatriz Otero, J. Manuel Moreno, X. Aragones, Israel Martin, Aleix Sole, Dunja Suttnig, Julia Calabro, Floriberto Lima, Eric Jouseau, François Cerisier, Cristian Rivier, Sepp Eisenriegler, Harald Reichl, Miroslav Macan, Dubravko Kruselj, Mladen Puskaric, Mirjana Tatalovic, Vinko Zelenicic, Bernd Deutschmann
2023 — conf
Design-Space Exploration of Mixed-precision DNN Accelerators based on Sum-Together Multipliers.
PRIME
Luca Urbinati, Mario R. Casu
2023 J jnl
Mix & Latch: An Optimization Flow for High-Performance Designs With Single-Clock Mixed-Polarity Latches and Flip-Flops.
IEEE Access
Filippo Minnella, Jordi Cortadella, Mario R. Casu, Mihai T. Lazarescu, Luciano Lavagno
2023 J jnl
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration.
CoRR
Fabrizio Ottati, Chang Gao, Qinyu Chen, Giovanni Brignone, Mario R. Casu, Jason K. Eshraghian, Luciano Lavagno
2023 J jnl
To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Fabrizio Ottati, Chang Gao, Qinyu Chen, Giovanni Brignone, Mario R. Casu, Jason K. Eshraghian, Luciano Lavagno
2022 — conf
A Reconfigurable 2D-Convolution Accelerator for DNNs Quantized with Mixed-Precision.
ApplePies
Luca Urbinati, Mario R. Casu
2022 C conf
A Reconfigurable Depth-Wise Convolution Module for Heterogeneously Quantized DNNs.
ISCAS
Luca Urbinati, Mario R. Casu
2022 J jnl
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu
2022 C conf
HLS-based dataflow hardware architecture for Support Vector Machine in FPGA.
ISCAS
Mohammad Amir Mansoori, Mario R. Casu
2022 — conf
Multi-objective Framework for Training and Hardware Co-optimization in FPGAs.
ApplePies
Mohammad Amir Mansoori, Mario R. Casu
2021 J jnl
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu
2021 — conf
Efficient Training and Hardware Co-design of Machine Learning Models.
ApplePies
Mohammad Amir Mansoori, Mario R. Casu
2021 J jnl
FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS.
IEEE Access
Mohammad Amir Mansoori, Pan Lu, Mario R. Casu
2021 J jnl
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs.
IEEE Access
Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno
2021 J jnl
Machine-Learning-Based Microwave Sensing: A Case Study for the Food Industry.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Marco Ricci, Bernardita Stitic, Luca Urbinati, Giuseppe Di Guglielmo, Jorge A. Tobon Vasquez, Luca P. Carloni, Francesca Vipiana, Mario R. Casu
2020 C conf
A Machine-Learning Based Microwave Sensing Approach to Food Contaminant Detection.
ISCAS
Luca Urbinati, Marco Ricci, Giovanna Turvani, Jorge A. Tobon Vasquez, Francesca Vipiana, Mario R. Casu
2020 J jnl
A Prototype Microwave System for 3D Brain Stroke Imaging.
Sensors
Jorge A. Tobon, Rosa Scapaticci, Giovanna Turvani, Gennaro Bellizzi, David O. Rodriguez-Duarte, Nadine Joachimowicz, Bernard Duchêne, Enrico Tedeschi, Mario R. Casu, Lorenzo Crocco, Francesca Vipiana
2020 J jnl
Power-Optimal Mapping of CNN Applications to Cloud-Based Multi-FPGA Platforms.
IEEE Trans. Circuits Syst.
Junnan Shan, Mihai T. Lazarescu, Jordi Cortadella, Luciano Lavagno, Mario R. Casu
2019 — conf
Efficient FPGA Implementation of PCA Algorithm for Large Data using High Level Synthesis.
PRIME
Mohammad Amir Mansoori, Mario R. Casu
2019 A* conf
Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA Platforms.
DAC
Junnan Shan, Mario R. Casu, Jordi Cortadella, Luciano Lavagno, Mihai T. Lazarescu
2019 — conf
HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC.
NORCAS
Mohammad Amir Mansoori, Mario R. Casu
2018 C conf
Design-Space Exploration of Pareto-Optimal Architectures for Deep Learning with DVFS.
ISCAS
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018 A conf
Energy-performance design exploration of a low-power microprogrammed deep-learning accelerator.
DATE
Giulia Santoro, Mario R. Casu, Valentino Peluso, Andrea Calimera, Massimo Alioto
2018 J jnl
Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.
Sensors
Francesco Dell'Anna, Tao Dong, Ping Li, Yumei Wen, Mehdi Azadmehr, Mario R. Casu, Yngvar Berg
2017 J jnl
A COTS-Based Microwave Imaging System for Breast-Cancer Detection.
IEEE Trans. Biomed. Circuits Syst.
Mario R. Casu, Marco Vacca, Jorge A. Tobon, Azzurra Pulimeno, Imran Sarwar, Raffaele Solimene, Francesca Vipiana
2017 J jnl
Accelerators for Breast Cancer Detection.
ACM Trans. Embed. Comput. Syst.
Daniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni
2017 — conf
ICARO-PAPM: Congestion Management with Selective Queue Power-Gating.
HPCS
José V. Escamilla, José Flich, Mario R. Casu
2017 J jnl
Power-performance assessment of different DVFS control policies in NoCs.
J. Parallel Distributed Comput.
Mario R. Casu, Paolo Giaccone
2016 — conf
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy.
MCSoC
José V. Escamilla, Mario R. Casu, José Flich
2015 — conf
A low-cost, fast, and accurate microwave imaging system for breast cancer detection.
BioCAS
Daniele Jahier Pagliari, Azzurra Pulimeno, Marco Vacca, Jorge A. Tobon, Francesca Vipiana, Mario R. Casu, Raffaele Solimene, Luca P. Carloni
2015 J jnl
A synchronous latency-insensitive RISC for better than worst-case design.
Integr.
Mario R. Casu, Paolo Mantovani
2015 C conf
Acceleration of microwave imaging algorithms for breast cancer detection via High-Level Synthesis.
ICCD
Daniele Jahier Pagliari, Mario R. Casu, Luca P. Carloni
2015 — conf
Microwave Imaging for Breast Cancer Detection: A COTS-Based Prototype.
ApplePies
Azzurra Pulimeno, Marco Vacca, Mario R. Casu, Jorge A. Tobon, Francesca Vipiana, Daniele Jahier Pagliari, Raffaele Solimene, Luca P. Carloni
2015 A conf
Rate-based vs delay-based control for DVFS in NoC.
DATE
Mario R. Casu, Paolo Giaccone
2014 J jnl
Accelerator Memory Reuse in the Dark Silicon Era.
IEEE Comput. Archit. Lett.
Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, Luca P. Carloni
2014 J jnl
Simulation and design of an UWB imaging system for breast cancer detection.
Integr.
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2014 J jnl
UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA?
ACM Trans. Embed. Comput. Syst.
Mario R. Casu, Francesco Colonna, Marco Crepaldi, Danilo Demarchi, Mariagrazia Graziano, Maurizio Zamboni
2013 — conf
Breast cancer detection based on an UWB imaging system: Receiver design and simulations.
ICICDT
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2013 — conf
Joint delay and power control in single-server queueing systems.
OnlineGreenComm
Andrea Bianco, Mario R. Casu, Paolo Giaccone, Marco Ricca
2013 J jnl
LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS.
IEEE Trans. Circuits Syst. II Express Briefs
Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
2013 — conf
UWB receiver for breast cancer detection: Comparison between two different approaches.
SoCC
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2012 — conf
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems.
ASYNC
Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
2011 J jnl
A NoC-based hybrid message-passing/shared-memory approach to CMP design.
Microprocess. Microsystems
Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni
2011 — conf
Coupling latency-insensitivity with variable-latency for better than worst case design: a RISC case study.
ACM Great Lakes Symposium on VLSI
Mario R. Casu, Stefano Colazzo, Paolo Mantovani
2011 J jnl
Half-buffer retiming and token cages for synchronous elastic circuits.
IET Comput. Digit. Tech.
Mario R. Casu
2010 A conf
A flexible UWB Transmitter for breast cancer detection imaging systems.
DATE
Massimo Cutrupi, Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano
2010 — conf
Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming.
ASYNC
Mario R. Casu
2010 A conf
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture.
DATE
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni
2009 J jnl
A Case Study for NoC-Based Homogeneous MPSoC Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni
2009 J jnl
A Fully Differential Digital CMOS UWB Pulse Generator.
Circuits Syst. Signal Process.
Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2009 J jnl
A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design.
Integr.
Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2009 — conf
Adaptive Latency Insensitive Protocols and Elastic Circuits with Early Evaluation: A Comparative Analysis.
FMGALS@DATE
Mario R. Casu, Luca Macchiarulo
2008 J jnl
A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mario R. Casu, Marco Crepaldi, Mariagrazia Graziano
2007 — conf
A methodology and a case-study for network-on-chip based MP-SoC architectures.
Nano-Net
Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
2007 J jnl
Adaptive Latency-Insensitive Protocols.
IEEE Des. Test Comput.
Mario R. Casu, Luca Macchiarulo
2007 A conf
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip.
DATE
Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
2007 — conf
The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology.
SoC
Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
2006 J jnl
Floorplanning With Wire Pipelining in Adaptive Communication Channels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mario R. Casu, Luca Macchiarulo
2006 — conf
Implementation analysis of NoC: a MPSoC trace-driven approach.
ACM Great Lakes Symposium on VLSI
Sergio Tota, Mario R. Casu, Luca Macchiarulo
2005 A conf
A New System Design Methodology for Wire Pipelined SoC.
DATE
Mario R. Casu, Luca Macchiarulo
2005 — conf
Floorplan assisted data rate enhancement through wire pipelining: a real assessment.
ISPD
Mario R. Casu, Luca Macchiarulo
2005 J jnl
Implementation aspects of a transmitted-reference UWB receiver.
Wirel. Commun. Mob. Comput.
Mario R. Casu, Giuseppe Durisi
2005 — conf
On the implementation of a transmitted-reference UWB receiver.
EUSIPCO
Mario R. Casu, Giuseppe Durisi, Sergio Benedetto
2005 J jnl
Throughput-driven floorplanning with wire pipelining.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mario R. Casu, Luca Macchiarulo
2004 A* conf
A new approach to latency insensitive design.
DAC
Mario R. Casu, Luca Macchiarulo
2004 J jnl
An electromigration and thermal model of power wires for a priori high-level reliability prediction.
IEEE Trans. Very Large Scale Integr. Syst.
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004 J jnl
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.
Microelectron. J.
Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2004 — conf
Floorplanning for throughput.
ISPD
Mario R. Casu, Luca Macchiarulo
2004 A conf
Issues in Implementing Latency Insensitive Protocols.
DATE
Mario R. Casu, Luca Macchiarulo
2004 C conf
On-Chip Transparent Wire Pipelining.
ICCD
Mario R. Casu, Luca Macchiarulo
2003 — conf
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.
PATMOS
M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003 J jnl
Coupled electro-thermal modeling and optimization of clock networks.
Microelectron. J.
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
2003 — conf
Effects of Temperature in Deep-Submicron Global Interconnect Optimization.
PATMOS
Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
2002 — conf
Clock Distribution Network Optimization under Self-Heating and Timing Constraints.
PATMOS
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
2002 — conf
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.
MTDT
Mario R. Casu, Philippe Flatresse
2001 A conf
Synthesis of low-leakage PD-SOI circuits with body-biasing.
ISLPED
Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni