Mario García-Valderas

43 papers A 1B 3C 16Journal 11Unranked 12

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A Comparison of Frequency-to-Digital Conversion Architectures in VCO-ADCs Built with Standard Cells. DCIS Alba Páez-Montoro, Celia López-Ongil, Mario García-Valderas, Susana Patón
2024	J	`jnl`	Analysing the radiation reliability, performance and energy consumption of low-power SoC through heterogeneous parallelism. Sustain. Comput. Informatics Syst. José M. Badía, German Leon, Mario García-Valderas, Jose A. Belloch, Almudena Lindoso, Luis Entrena
2024	—	`conf`	Power Oriented Hardware-Software Codesign for a Planetary Exploration Multisensor Instrument. DCIS Alberto Ramírez-Bárcenas, Mario García-Valderas, Celia López-Ongil
2023	—	`conf`	Design Space Analysis for a Digital Lock-In Amplifier for Infrared Gas Sensor Signal Acquisition. DCIS Alberto Ramírez-Bárcenas, Mario García-Valderas, Celia López-Ongil
2023	J	`jnl`	Formal Verification of Fault-Tolerant Hardware Designs. IEEE Access Luis Entrena, Antonio J. Sanchez-Clemente, Luis Ángel García-Astudillo, Marta Portela-García, Mario García-Valderas, Almudena Lindoso, Roberto Sarmiento
2022	—	`conf`	Low Power Consumption Online Testing Technique for Wearable Wireless Body Area Networks. DCIS Iñigo Mikel Lasaga Arana, Alberto Ramírez-Bárcenas, Mario García-Valderas, Celia López-Ongil
2022	J	`jnl`	Solar Energy Harvesting to Improve Capabilities of Wearable Devices. Sensors Alba Páez-Montoro, Mario García-Valderas, Emilio Olías-Ruíz, Celia López-Ongil
2020	—	`conf`	System Dependability in Edge Computing Wearable Devices. DCIS Alberto Ramírez-Bárcenas, Marta Portela-García, Mario García-Valderas, Celia López-Ongil
2019	—	`conf`	Assessing SET Sensitivity of Mixed-Signal Circuits at Early Design Stages. DCIS Aranzazu Fernandez-Alvarez, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Samuel Sordo Ibáñez, Servando Espejo-Meana
2018	—	`conf`	Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals. DCIS José Angel Miranda Calero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Mario García-Valderas, Celia López-Ongil
2018	J	`jnl`	PTM-based hybrid error-detection architecture for ARM microprocessors. Microelectron. Reliab. Manuel Peña-Fernandez, Almudena Lindoso, Luis Entrena, Mario García-Valderas, S. Philippe, Yolanda Morilla, Pedro Martín-Holgado
2017	C	`conf`	On-line testing of sensor networks: A case study. IOLTS José Angel Miranda, Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil
2014	J	`jnl`	A method to assess the robustness of cryptographic circuits at the design stage. Microelectron. J. M. Arévalo-Garbayo, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
2014	C	`conf`	Error masking with approximate logic circuits using dynamic probability estimations. IOLTS Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas
2014	C	`conf`	Permanent faults on LIN networks: On-line test generation. IOLTS Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda
2014	—	`conf`	Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques. LATW Anna Vaskova, A. Fabregat, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Matteo Sonza Reorda
2012	J	`jnl`	Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach. J. Electron. Test. Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, N. Marroni, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
2012	C	`conf`	Logic masking for SET Mitigation Using Approximate Logic Circuits. IOLTS Antonio Sanchez-Clemente, Luis Entrena, Mario García-Valderas, Celia López-Ongil
2012	J	`jnl`	On the use of embedded debug features for permanent and transient fault resilience in microprocessors. Microprocess. Microsystems Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil
2012	C	`conf`	SEU sensitivity of robust communication protocols. IOLTS Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Anna Vaskova, Luis Entrena, Joaquín Rivas-Abalo, Alberto Martín-Ortega, Javier Martinez-Oter, S. Rodriguez-Bustabad, Ignacio Arruego
2012	J	`jnl`	Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection. IEEE Trans. Computers Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil
2011	C	`conf`	Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. IOLTS Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena
2011	J	`jnl`	Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. IEEE Trans. Dependable Secur. Comput. Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2011	—	`conf`	Using an FPGA-based fault injection technique to evaluate software robustness under SEEs: A case study. LATW Marta Portela-García, Almudena Lindoso, Luis Entrena, Mario García-Valderas, Celia López-Ongil, Bernardo Pianta, Letícia Maria Bolzani Poehls, Fabian Vargas
2010	C	`conf`	An on-line fault detection technique based on embedded debug features. IOLTS Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena
2009	C	`conf`	Briefing power/reliability optimization in embedded software design. IOLTS Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2009	C	`conf`	In-depth analysis of digital circuits against soft errors for selective hardening. IOLTS Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
2009	C	`conf`	Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. IOLTS Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena
2009	J	`jnl`	SET Emulation Under a Quantized Delay Model. J. Electron. Test. Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García
2009	—	`conf`	Study of SEU effects in a Turbo Decoder Bit Error Rate. LATW Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena, B. Lestriez, Luis Berrojo
2008	C	`conf`	Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. IOLTS Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena
2007	C	`conf`	A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. IOLTS Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena
2007	—	`conf`	SET Emulation Under a Quantized Delay Model. DFT Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena
2007	J	`jnl`	Techniques for Fast Transient Fault Grading Based on Autonomous Emulation CoRR Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
2006	C	`conf`	An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. DDECS Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes
2006	C	`conf`	Emulation-based Fault Injection in Circuits with Embedded Memories. IOLTS Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena
2006	—	`conf`	Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets. LATW S. Torrellas, Bogdan Nicolescu, Raul Velazco, Mario García-Valderas, Yvon Savaria
2005	B	`conf`	An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. FPL Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
2005	C	`conf`	Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. IOLTS Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
2005	A	`conf`	Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. DATE Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes
2004	B	`conf`	Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo
2004	B	`conf`	Power Consumption Reduction Through Dynamic Reconfiguration. FPL Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena
2004	C	`conf`	Transient Fault Emulation of Hardened Circuits in FPGA Platforms. IOLTS Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena