Marie-Lise Flottes

142 papers A 10B 12C 22Misc 4Journal 37Unranked 56

Year	Rank	Type	Title / Venue / Authors
2024	A	`conf`	A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. DATE Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2024	—	`conf`	Logic Locking: Exploration of a new key-gate based on tristate logic. LATS Sophie Dupuis, Nassim Riadi, Clémy Moroukian, Florence Azaïs, Marie-Lise Flottes
2024	B	`conf`	Power Analysis Attack Against post-SAT Logic Locking schemes. ETS Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes
2024	J	`jnl`	Utilizing Layout Effects for Analog Logic Locking. CoRR Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
2024	J	`jnl`	Utilizing layout effects for analog logic locking. J. Cryptogr. Eng. Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
2023	J	`jnl`	Hybrid Protection of Digital FIR Filters. CoRR Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2023	J	`jnl`	Hybrid Protection of Digital FIR Filters. IEEE Trans. Very Large Scale Integr. Syst. Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2023	B	`conf`	Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture. ETS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel, Arnaud Virazel
2023	—	`conf`	Resynthesis-based Attacks Against Logic Locking. ISQED Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
2023	J	`jnl`	Resynthesis-based Attacks Against Logic Locking. CoRR Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini
2022	B	`conf`	A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing. ETS S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
2022	—	`conf`	Leveraging Layout-based Effects for Locking Analog ICs. ASHES@CCS Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
2022	J	`jnl`	Leveraging Layout-based Effects for Locking Analog ICs. CoRR Muayad J. Aljafar, Florence Azaïs, Marie-Lise Flottes, Samuel Pagliarini
2021	B	`conf`	A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices. ETS S. Lapeyre, Nicolas Valette, Marc Merandat, Marie-Lise Flottes, Bruno Rouzeyre, Arnaud Virazel
2021	C	`conf`	High-level Intellectual Property Obfuscation via Decoy Constants. IOLTS Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2021	J	`jnl`	High-level Intellectual Property Obfuscation via Decoy Constants. CoRR Levent Aksoy, Quang-Linh Nguyen, Felipe Almeida, Jaan Raik, Marie-Lise Flottes, Sophie Dupuis, Samuel Pagliarini
2021	—	`conf`	On Preventing SAT Attack with Decoy Key-Inputs. ISVLSI Quang-Linh Nguyen, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
2021	—	`conf`	Preliminary Defect Analysis of 8T SRAM Cells for In-Memory Computing Architectures. DTIS Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Arnaud Virazel
2020	C	`conf`	A Secure Scan Controller for Protecting Logic Locking. IOLTS Quang-Linh Nguyen, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
2020	C	`conf`	Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs. IOLTS Florence Azaïs, Serge Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard, Vincent Kerzèrho, Laurent Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssade, Arnaud Virazel
2019	—	`conf`	A Comprehensive Approach to a Trusted Test Infrastructure. IVSW Marc Merandat, Vincent Reynaud, Emanuele Valea, Jérôme Quévremont, Nicolas Valette, Paolo Maistri, Régis Leveugle, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre, Giorgio Di Natale
2019	J	`jnl`	A Survey on Security Threats and Countermeasures in IEEE Test Standards. IEEE Des. Test Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2019	C	`conf`	Encryption-Based Secure JTAG. DDECS Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2019	J	`jnl`	Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. J. Electron. Test. Sophie Dupuis, Marie-Lise Flottes
2019	J	`jnl`	Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2019	—	`conf`	Providing Confidentiality and Integrity in Ultra Low Power IoT Devices. DTIS Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Sophie Dupuis, Bruno Rouzeyre
2019	J	`jnl`	SECCS: SECure Context Saving for IoT Devices. CoRR Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
2019	J	`jnl`	Stream vs block ciphers for scan encryption. Microelectron. J. Emanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2018	—	`conf`	A New Secure Stream Cipher for Scan Chain Encryption. IVSW Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
2018	J	`jnl`	Assessing body built-in current sensors for detection of multiple transient faults. Microelectron. Reliab. Raphael Andreoni Camponogara Viera, Jean-Max Dutertre, Marie-Lise Flottes, Olivier Potin, Giorgio Di Natale, Bruno Rouzeyre, Rodrigo Possamai Bastos
2018	—	`conf`	Encryption of test data: which cipher is better? PRIME Mathieu Da Silva, Emanuele Valea, Marie-Lise Flottes, Sophie Dupuis, Giorgio Di Natale, Bruno Rouzeyre
2018	C	`conf`	Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model. FDTC Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Stephan De Castro, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
2018	J	`jnl`	Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead. IEEE Des. Test Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2018	—	`conf`	SI ECCS: SECure context saving for IoT devices. DTIS Emanuele Valea, Mathieu Da Silva, Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
2018	C	`conf`	The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks. IOLTS Jean-Max Dutertre, Vincent Beroulle, Philippe Candelier, Louis-Barthelemy Faber, Marie-Lise Flottes, Philippe Gendrier, David Hély, Régis Leveugle, Paolo Maistri, Giorgio Di Natale, Athanasios Papadimitriou, Bruno Rouzeyre
2017	—	`conf`	Experimentations on scan chain encryption with PRESENT. IVSW Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2017	—	`conf`	Hacking the Control Flow error detection mechanism. IVSW Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre
2017	B	`conf`	Scan chain encryption for the test, diagnosis and debug of secure circuits. ETS Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Paolo Prinetto, Marco Restifo
2016	J	`jnl`	Frontside Versus Backside Laser Injection: A Comparative Study. ACM J. Emerg. Technol. Comput. Syst. Stephan De Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes
2016	—	`conf`	Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2016	—	`conf`	Using outliers to detect stealthy hardware trojan triggering? IVSW Papa-Sidy Ba, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2015	—	`conf`	3D DFT Challenges and Solutions. ISVLSI Yassine Fkih, Pascal Vivet, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Juergen Schloeffel
2015	—	`conf`	Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits. ISVLSI Stephan De Castro, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Jean-Max Dutertre
2015	—	`conf`	Hardware Trojan prevention using layout-level design approach. ECCTD Papa-Sidi Ba, Palanichamy Manikandan, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2015	A	`conf`	New testing procedure for finding insertion sites of stealthy hardware trojans. DATE Sophie Dupuis, Papa-Sidi Ba, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2015	—	`conf`	On the limitations of logic testing for detecting Hardware Trojans Horses. DTIS Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre
2015	B	`conf`	Session-less based thermal-aware 3D-SIC test scheduling. ETS Marie-Lise Flottes, Joao Azevedo, Giorgio Di Natale, Bruno Rouzeyre
2014	—	`conf`	2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures. ISVLSI Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale, Juergen Schloeffel
2014	C	`conf`	A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans. IOLTS Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2014	Misc	`conf`	Built-in self-test for manufacturing TSV defects before bonding. VTS Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche
2014	C	`conf`	Customized cell detector for laser-induced-fault detection. IOLTS Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2014	J	`jnl`	Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS. Microelectron. Reliab. Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale, Alexandre Sarafianos
2014	—	`conf`	Laser attacks on integrated circuits: From CMOS to FD-SOI. DTIS Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noemie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale
2014	—	`conf`	Laser-Induced Fault Effects in Security-Dedicated Circuits. VLSI-SoC (Selected Papers) Vincent Beroulle, Philippe Candelier, Stephan De Castro, Giorgio Di Natale, Jean-Max Dutertre, Marie-Lise Flottes, David Hély, Guillaume Hubert, Régis Leveugle, Feng Lu, Paolo Maistri, Athanasios Papadimitriou, Bruno Rouzeyre, Clément Tavernier, Pierre Vanhauwaert
2014	C	`conf`	Laser-induced fault effects in security-dedicated circuits. VLSI-SoC Régis Leveugle, Paolo Maistri, Pierre Vanhauwaert, Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Guillaume Hubert, Stephan De Castro, Jean-Max Dutertre, Alexandre Sarafianos, Noemie Boher, Mathieu Lisart, Joel Damiens, Philippe Candelier, Clément Tavernier
2014	—	`conf`	Layout-aware laser fault injection simulation and modeling: From physical level to gate level. DTIS Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Guillaume Hubert
2014	J	`jnl`	Test Versus Security: Past and Present. IEEE Trans. Emerg. Top. Comput. Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2014	J	`jnl`	Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison. IEEE Trans. Very Large Scale Integr. Syst. Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	—	`conf`	A 3D IC BIST for pre-bond test of TSVs using ring oscillators. NEWCAS Yassine Fkih, Pascal Vivet, Bruno Rouzeyre, Marie-Lise Flottes, Giorgio Di Natale
2013	—	`conf`	A BIST method for TSVs pre-bond test. IDT Hakim Zimouche, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	J	`jnl`	A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic. J. Electron. Test. Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Feng Lu, Bruno Rouzeyre
2013	—	`conf`	A bulk built-in sensor for detection of fault attacks. HOST Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2013	J	`jnl`	A novel differential scan attack on advanced DFT structures. ACM Trans. Design Autom. Electr. Syst. Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	—	`conf`	A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults. PATMOS Rodrigo Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre
2013	C	`conf`	A smart test controller for scan chains in secure circuits. IOLTS Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	C	`conf`	Laser-Induced Fault Simulation. DSD Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	J	`jnl`	Multilevel Ionizing-Induced Transient Fault Simulator. Inf. Secur. J. A Glob. Perspect. Feng Lu, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	J	`jnl`	On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis. Inf. Secur. J. A Glob. Perspect. Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2013	J	`jnl`	Secure JTAG Implementation Using Schnorr Protocol. J. Electron. Test. Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2013	J	`jnl`	Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection. Microelectron. Reliab. Jean-Max Dutertre, Rodrigo Possamai Bastos, Olivier Potin, Marie-Lise Flottes, Bruno Rouzeyre, Giorgio Di Natale
2012	—	`conf`	A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2012	—	`conf`	A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. DFT Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2012	Misc	`conf`	Are advanced DfT structures sufficient for preventing scan-attacks? VTS Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2012	J	`jnl`	Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. Microelectron. Reliab. Rodrigo Possamai Bastos, Frank Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2012	—	`ch.`	On Countermeasures Against Fault Attacks on the Advanced Encryption Standard. Fault Analysis in Cryptography Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2012	B	`conf`	On-chip test comparison for protecting confidential data in secure ICs. ETS Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2012	J	`jnl`	Scan attacks on side-channel and fault attack resistant public-key implementations. J. Cryptogr. Eng. Jean DaRolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede
2011	—	`conf`	A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2011	—	`conf`	New security threats against chips containing scan chain structures. HOST Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2011	C	`conf`	Power consumption traces realignment to improve differential power analysis. DDECS Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal
2011	B	`conf`	Scan Attacks and Countermeasures in Presence of Scan Response Compactors. ETS Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2011	—	`conf`	Timing issues for an efficient use of concurrent error detection codes. LATW Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2010	C	`conf`	Ensuring high testability without degrading security: Embedded tutorial on "test and security". DDECS Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2010	—	`conf`	Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2010	B	`conf`	Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. ETS Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2010	C	`conf`	Evaluation of concurrent error detection techniques on the advanced encryption standard. IOLTS Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2010	J	`jnl`	Self-Test Techniques for Crypto-Devices. IEEE Trans. Very Large Scale Integr. Syst. Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
2009	J	`jnl`	A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. J. Electron. Test. Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
2009	—	`conf`	Execution time reduction of Differential Power Analysis experiments. LATW Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2009	J	`jnl`	Remote Labs for Industrial IC Testing. IEEE Trans. Learn. Technol. Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet
2008	B	`conf`	A Reliable Architecture for the Advanced Encryption Standard. ETS Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
2008	—	`conf`	AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre
2008	—	`conf`	An Integrated Validation Environment for Differential Power Analysis. DELTA Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2008	—	`conf`	Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre
2008	A	`conf`	Wireless Test Structure for Integrated Systems. ITC Ziad Noun, Philippe Cauvet, Marie-Lise Flottes, David Andreu, Serge Bernard
2007	—	`conf`	A Dependable Parallel Architecture for SBoxes. ReCoSoC Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2007	C	`conf`	A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2007	C	`conf`	An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre
2007	—	`conf`	Compression-based SoC Test Infrastructures. VLSI-SoC (Selected Papers) Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
2007	J	`jnl`	Mutation Sampling Technique for the Generation of Structural Test Data CoRR Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
2007	J	`jnl`	Securing Scan Control in Crypto Chips. J. Electron. Test. David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2007	C	`conf`	Test data compression and TAM design. VLSI-SoC Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
2006	A	`conf`	A secure scan design methodology. DATE David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2006	—	`conf`	Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre
2006	—	`conf`	Scan Pattern Watermarking. LATW David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2006	C	`conf`	Secure Scan Techniques: A Comparison. IOLTS David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2005	A	`conf`	Mutation Sampling Technique for the Generation of Structural Test Data. DATE Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre
2005	—	`conf`	Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project. EDUTECH Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes
2005	B	`conf`	Test control for secure scan designs. ETS David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre
2004	A	`conf`	An Arithmetic Structure for Test Data Horizontal Compression. DATE Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
2004	—	`conf`	Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ. DELTA Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich
2004	—	`conf`	On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
2004	C	`conf`	Scan Design and Secure Chip. IOLTS David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
2004	B	`conf`	User-constrained test architecture design for modular SOC testing. ETS Ludovic A. Krundel, Sandeep Kumar Goel, Erik Jan Marinissen, Marie-Lise Flottes, Bruno Rouzeyre
2003	J	`jnl`	A Unified DFT Approach for BIST and External Test. J. Electron. Test. Marie-Lise Flottes, Christian Landrault, A. Petitqueux
2003	—	`conf`	An efficient approach to SoC wrapper design, TAM configuration and test scheduling. ETW Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre
2003	—	`conf`	Test Engineering Education in Europe: the EuNICE-Test Project. MSE Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden
2002	A	`conf`	A Heuristic for Test Scheduling at System Level. DATE Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
2002	—	`conf`	A simple and effective compression scheme for test pins reduction. HLDVT Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre
2002	—	`conf`	European Network for Test Education. DELTA Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival
2002	J	`jnl`	Improving Datapath Testability by Modifying Controller Specification. VLSI Design Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe
2002	C	`ed.`	SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France VLSI-SOC Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes
2001	J	`jnl`	A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electron. Test. David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
2001	C	`conf`	Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre
2000	C	`conf`	A controller resynthesis based method for improving datapath testability. ISCAS Marie-Lise Flottes, Bruno Rouzeyre, Laurent Volpe
2000	—	`conf`	A method for trading off test time, area and fault coverage in datapath BIST synthesis. ETW David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
2000	A	`conf`	BISTing data paths at behavioral level. ITC David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
2000	—	`conf`	Design for sequential testability: an internal state reseeding approach for 100 % fault coverage. Asian Test Symposium Marie-Lise Flottes, Christian Landrault, A. Petitqueux
1999	—	`conf`	A Successful Distance-Learning Experience for IC Test Education. MSE Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival
1999	J	`jnl`	BISTing Datapaths under Heterogeneous Test Schemes. J. Electron. Test. David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
1999	—	`conf`	Partial set for flip-flops based on state requirement for non-scan BIST scheme. ETW Marie-Lise Flottes, Christian Landrault, A. Petitqueux
1998	—	`conf`	Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium Marie-Lise Flottes, R. Pires, Bruno Rouzeyre
1998	Misc	`conf`	Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe
1998	A	`conf`	Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe
1997	—	`conf`	Analyzing testability from behavioral to RT level. ED&TC Marie-Lise Flottes, R. Pires, Bruno Rouzeyre
1997	J	`jnl`	Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electron. Test. Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre
1995	—	`conf`	High-level synthesis for easy testability. ED&TC Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre
1995	A	`conf`	Is High-Level Test Synthesis Just Design for Test? ITC Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre
1994	—	`conf`	Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre
1992	Misc	`conf`	A New Reliable Method for Delay-Fault Diagnosis. VLSI Design Marie-Lise Flottes, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
1991	J	`jnl`	Fault modeling and fault equivalence in CMOS technology. J. Electron. Test. Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch
1990	—	`conf`	Fault modelling and fault equivalence in CMOS technology. EURO-DAC Marie-Lise Flottes, Christian Landrault, Serge Pravossoudovitch