Marcus Bednara

13 papers A 5Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Accelerating Linear Programming Performance: A Hardware-Software Co-Design Approach for the Simplex Method. HEART Marcus Bednara, Kristin Braun, Martina Kuchlbauer, Carsten Sigwarth
2018	—	`conf`	Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker
2017	A	`conf`	WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker
2004	A	`conf`	A New Approach for On-line Placement on Reconfigurable Devices. IPDPS Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
2004	A	`conf`	Real-Time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. IPDPS Ali Ahmadinia, Christophe Bobda, Marcus Bednara, Jürgen Teich
2003	A	`conf`	A High Performance VLIW Processor for Finite Field Arithmetic. IPDPS Cornelia Grabbe, Marcus Bednara, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
2003	J	`jnl`	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms. J. Supercomput. Marcus Bednara, Jürgen Teich
2003	J	`jnl`	Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware. EURASIP J. Adv. Signal Process. Marcus Bednara, Klaus Danne, Markus Deppe, Oliver Oberschelp, Frank Slomka, Jürgen Teich
2003	—	`conf`	FPGA designs of parallel high performance GF(2 ISCAS (2) Cornelia Grabbe, Marcus Bednara, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
2002	—	`conf`	Generation of Distributed Loop Control. Embedded Processor Design Challenges Marcus Bednara, Frank Hannig, Jürgen Teich
2002	A	`conf`	Reconfigurable Implementation of Elliptic Curve Crypto Algorithms. IPDPS Marcus Bednara, M. Daldrup, Joachim von zur Gathen, Jamshid Shokrollahi, Jürgen Teich
2002	—	`conf`	Tradeoff analysis of FPGA based elliptic curve cryptography. ISCAS (5) Marcus Bednara, M. Daldrup, Jürgen Teich, Joachim von zur Gathen, Jamshid Shokrollahi
2000	—	`conf`	Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter. ASAP Marcus Bednara, Oliver Beyer, Jürgen Teich, Rolf Wanka