Marco Zanuso

14 papers C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2011 J jnl
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs
IEEE J. Solid State Circuits
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011 — conf
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.
ISSCC
Davide Tasca, Marco Zanuso, Giovanni Marzin, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011 J jnl
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.
IEEE J. Solid State Circuits
Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011 J jnl
Low-Power Divider Retiming in a 3-4 GHz Fractional-N PLL.
IEEE Trans. Circuits Syst. II Express Briefs
Davide Tasca, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2011 C conf
Multipath adaptive cancellation of divider non-linearity in fractional-N PLLs.
ISCAS
Carlo Samori, Marco Zanuso, Salvatore Levantino, Andrea L. Lacaita
2010 — conf
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.
ISSCC
Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2010 J jnl
AD-PLL for WiMAX with Digitally-Regulated TDC and Glitch Correction Logic.
EURASIP J. Embed. Syst.
Salvatore Levantino, Marco Zanuso, Paolo Madoglio, Davide Tasca, Carlo Samori, Andrea L. Lacaita
2010 — conf
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.
ISSCC
Salvatore Levantino, Marco Zanuso, Carlo Samori, Andrea L. Lacaita
2010 J jnl
Time-to-Digital Converter for Frequency Synthesis Based on a Digital Bang-Bang DLL.
IEEE Trans. Circuits Syst. I Regul. Pap.
Marco Zanuso, Paolo Madoglio, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita
2010 — conf
Time-to-digital converter with 3-ps resolution and digital linearization algorithm.
ESSCIRC
Marco Zanuso, Salvatore Levantino, Alberto Puggelli, Carlo Samori, Andrea L. Lacaita
2009 — conf
A glitch-corrector circuit for low-spur ADPLLs.
ICECS
Marco Zanuso, Salvatore Levantino, Davide Tasca, Daniele Raiteri, Carlo Samori, Andrea L. Lacaita
2009 — conf
An all-digital architecture for low-jitter regulated delay lines.
ICECS
Salvatore Levantino, Marco Zanuso, Davide Tasca, Carlo Samori, Andrea L. Lacaita
2009 J jnl
Noise Analysis and Minimization in Bang-Bang Digital PLLs.
IEEE Trans. Circuits Syst. II Express Briefs
Marco Zanuso, Davide Tasca, Salvatore Levantino, Andrea Donadel, Carlo Samori, Andrea L. Lacaita
2007 J jnl
Quantization Effects in All-Digital Phase-Locked Loops.
IEEE Trans. Circuits Syst. II Express Briefs
Paolo Madoglio, Marco Zanuso, Salvatore Levantino, Carlo Samori, Andrea L. Lacaita