Marco Sosio

22 papers C 1Journal 10Unranked 11
YearRankTypeTitle / Venue / Authors
2026 — conf
23.2 A 2-Channel 800Gb/s Transceiver for Coherent-Lite Applications with <300ns Latency in 5nm FinFET.
ISSCC
Marco Sosio, Claudio Nani, Enrico Monaco, Nicola Ghittori, Domenico Albano, Alessio Di Pasquo, Alessandro Bosi, Travis Lovitt, Gabriele Gira, Fulvio Martinelli, Victor Karam, Devrishi Khanna, Mehdi N. Khiarak, Sasan Cyrusian, Mehdi Davoodi, Marco Garampazzi, Nimesh N. Miral, Fabio Giunco, Ivan Fabiano, Nicola Codega, Claudio Asero, Leonardo Daniel Herbas Burgos, Enrico Temporiti, Shawn Scouten, Kishore Kota, Yang Fu, Ruibin Jin, Josef Mueller, Michael Leung, Arash Farhoodfar, Stephen Jantzi, Ken Chang
2025 J jnl
A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz.
IEEE J. Solid State Circuits
Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2025 J jnl
An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process.
IEEE J. Solid State Circuits
Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, Domenico Albano, Claudio Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, Leonardo Daniel Herbas Burgos, Stanley S. K. Ho, Enrico Monaco, Benjamín T. Reyes, Paolo Rossi, Enrico Temporiti, Paolo Pascale, Fernando De Bernardinis, Shawn Scouten, Stephen Jantzi
2024 — conf
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.
VLSI Technology and Circuits
Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi
2024 — conf
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process.
VLSI Technology and Circuits
Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi
2022 — conf
An Integrated Low-power 802.11ba Wake-up Radio for IoT with Embedded Microprocessor.
ICECS 2022
Marco Ronchi, Francesco Malena, Michele Caselli, Devis Gatti, Ermano Picco, Elena Salurso, Marco Sosio, Lucio Ticli, Alessandro Tomasoni, Eusebio Di-Cola, Tommaso Majo, Fabio Osnato, Elio Guidetti, Andrea Boni
2020 J jnl
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.
IEEE J. Solid State Circuits
Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani
2019 — conf
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
ISSCC
Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti
2018 C conf
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers.
ISCAS
Alessandro Truppi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino, Marco Ronchi, Marco Sosio
2013 J jnl
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS.
IEEE J. Solid State Circuits
Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Samuel Er-Shen Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello
2013 J jnl
An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory.
IEEE Trans. Circuits Syst. II Express Briefs
Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013 J jnl
SAW-Less Analog Front-End Receivers for TDD and FDD.
IEEE J. Solid State Circuits
Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2013 — conf
SAW-less analog front-end receivers for TDD and FDD.
ISSCC
Ivan Fabiano, Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012 J jnl
A 2G/3G Cellular Analog Baseband Based on a Filtering ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Marco Sosio, Antonio Liscidini, Rinaldo Castello
2012 — conf
A 40MHz-to-1GHz fully integrated multistandard silicon tuner in 80nm CMOS.
ISSCC
Jody Greenberg, Fernando De Bernardinis, Carlo Tinella, Antonio Milani, Johnny Pan, Paola Uggetti, Marco Sosio, Shaoan Dai, Sam Tang, Giovanni Cesura, Gabriele Gandolfi, Vittorio Colonna, Rinaldo Castello
2011 J jnl
A 24 GHz Subharmonic Direct Conversion Receiver in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto
2011 — conf
A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC.
ESSCIRC
Marco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis
2010 J jnl
A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers.
IEEE J. Solid State Circuits
Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto
2009 — conf
A reconfigurable demodulator with 3-to-5GHz agile synthesizer for 9-band WiMedia UWB in 65nm CMOS.
ISSCC
Andrea Mazzanti, Mohammad B. Vahidfar, Marco Sosio, Francesco Svelto
2008 — conf
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS.
ISSCC
Andrea Mazzanti, Marco Sosio, Matteo Repossi, Francesco Svelto
2007 J jnl
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS.
IEEE J. Solid State Circuits
Massimo Brandolini, Marco Sosio, Francesco Svelto
2006 — conf
A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS.
ISSCC
Massimo Brandolini, Marco Sosio, Francesco Svelto