Marco Siracusa

18 papers A* 2A 2Misc 2Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2026 A conf
Ember: A Compiler for Embedding Operations on Decoupled Access-Execute Architectures.
CGO
Marco Siracusa, Olivia Hsu, Víctor Soria Pardos, Joshua Randall, Arnaud Grasset, Eric Biscondi, Douglas J. Joseph, Randy Allen, Fredrik Kjolstad, Miquel Moretó Planas, Adrià Armejach
2026 — conf
FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow.
ASPLOS (2)
Rubens Lacouture, Nathan Zhang, Ritvik Sharma, Marco Siracusa, Fredrik Kjolstad, Kunle Olukotun, Olivia Hsu
2025 J jnl
Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures.
CoRR
Marco Siracusa, Olivia Hsu, Víctor Soria Pardos, Joshua Randall, Arnaud Grasset, Eric Biscondi, Douglas J. Joseph, Randy Allen, Fredrik Kjolstad, Miquel Moretó Planas, Adrià Armejach
2025 J jnl
FuseFlow: A Fusion-Centric Compilation Framework for Sparse Deep Learning on Streaming Dataflow.
CoRR
Rubens Lacouture, Nathan Zhang, Ritvik Sharma, Marco Siracusa, Fredrik Kjolstad, Kunle Olukotun, Olivia Hsu
2024 J jnl
SpChar: Characterizing the sparse puzzle via decision trees.
J. Parallel Distributed Comput.
Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó
2023 A* conf
A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors.
MICRO
Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach
2023 J jnl
SpChar: Characterizing the Sparse Puzzle via Decision Trees.
CoRR
Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó
2022 J jnl
A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model.
IEEE Trans. Computers
Marco Siracusa, Emanuele Del Sozzo, Marco Rabozzi, Lorenzo Di Tucci, Samuel Williams, Donatella Sciuto, Marco Domenico Santambrogio
2022 J jnl
FPGA-based HPC accelerators: An evaluation on performance and energy efficiency.
Concurr. Comput. Pract. Exp.
Tan Nguyen, Colin MacLean, Marco Siracusa, Douglas Doerfler, Nicholas J. Wright, Samuel Williams
2021 — conf
Experiences Porting the SU3_Bench Microbenchmark to the Intel Arria 10 and Xilinx Alveo U280 FPGAs.
IWOCL
Douglas Doerfler, Farzad Fatollahi-Fard, Colin MacLean, Tan Nguyen, Samuel Williams, Nicholas J. Wright, Marco Siracusa
2021 A* conf
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs.
DAC
Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco D. Santambrogio
2021 J jnl
Scaling up HBM Efficiency of Top-K SpMV for Approximate Embedding Similarity on FPGAs.
CoRR
Alberto Parravicini, Luca Giuseppe Cellamare, Marco Siracusa, Marco Domenico Santambrogio
2021 Misc conf
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.
FCCM
Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco D. Santambrogio
2021 J jnl
Solving Large Top-K Graph Eigenproblems with a Memory and Compute-optimized FPGA Design.
CoRR
Francesco Sgherzi, Alberto Parravicini, Marco Siracusa, Marco Domenico Santambrogio
2020 A conf
A CAD-based methodology to optimize HLS code via the Roofline model.
ICCAD
Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Samuel Williams, Marco D. Santambrogio
2020 J jnl
Tensor Optimization for High-Level Synthesis Design Flows.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Marco Siracusa, Fabrizio Ferrandi
2020 — conf
The Performance and Energy Efficiency Potential of FPGAs in Scientific Computing.
PMBS@SC
Tan Nguyen, Samuel Williams, Marco Siracusa, Colin MacLean, Douglas Doerfler, Nicholas J. Wright
2019 Misc conf
Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications.
FCCM
Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Marco D. Santambrogio, Lorenzo Di Tucci