Marco Rios - RankMe

14 papers A 1C 2Misc 1Journal 6Unranked 4

Year	Rank	Type	Title / Venue / Authors
2023	C	`conf`	A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication. VLSI-SoC Grégoire Eggermann, Marco Rios, Giovanni Ansaloni, Sani R. Nassif, David Atienza
2023	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. IEEE Trans. Emerg. Top. Comput. Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2023	J	`jnl`	Overflow-free Compute Memories for Edge AI Acceleration. ACM Trans. Embed. Comput. Syst. Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2022	J	`jnl`	A Hardware/Software Co-Design Vision for Deep Learning at the Edge. IEEE Micro Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón-Quirós, David Atienza
2022	J	`jnl`	Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference. CoRR Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
2022	—	`conf`	Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge. ACM Great Lakes Symposium on VLSI Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2021	—	`conf`	A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs. ISVLSI Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2021	A	`conf`	Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. DATE Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza
2020	J	`jnl`	BLADE: An in-Cache Computing Architecture for Edge Devices. IEEE Trans. Computers William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
2020	Misc	`conf`	Exploration Methodology for BTI-Induced Failures on RRAM-Based Edge AI Systems. ICASSP Alexandre Levisse, Marco Rios, Miguel Peón-Quirós, David Atienza
2020	—	`conf`	RRAM-VAC: A Variability-Aware Controller for RRAM-based Memory Architectures. ASP-DAC Shikhar Tuli, Marco Rios, Alexandre Levisse, David Atienza
2020	J	`jnl`	Write Termination Circuits for RRAM: A Holistic Approach From Technology to Application Considerations. IEEE Access Alexandre Levisse, Marc Bocquet, Marco Rios, Mouhamad Alayan, Mathieu Moreau, Etienne Nowak, Gabriel Molas, Elisa Vianello, David Atienza, Jean-Michel Portal
2019	C	`conf`	An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication. VLSI-SoC Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
2019	—	`conf`	Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza