Marco Re - RankMe

121 papers A 1B 1C 17Misc 9Journal 26Unranked 67

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Exploring the Limits of High-Throughput Wideband Digital Signal Processing on AMD Versal AI Engines and Programmable Logic: Insights from a Polyphase Filter Bank Deployment. IEEECONF Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Riccardo La Cesa, Marco Re, Sergio Spanò, Cristian Valenti
2025	J	`jnl`	High efficiency hardware implementation of a ZP-OTFS modulator for next generation high-mobility wireless systems. Comput. Electr. Eng. Riccardo La Cesa, Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Sergio Spanò, Cristian Valenti
2024	J	`jnl`	A Novel Digital Equalizer Based on RF Sampling Beyond GHz. IEEE Access Lorenzo Canese, Gian Carlo Cardarilli, Riccardo La Cesa, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò
2024	—	`conf`	Automatic Tunable Floating-Point Format Selection in a RISC-V Ecosystem. ApplePies Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, Sergio Spanò
2024	J	`jnl`	Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey. IEEE Access Stefano Bertazzoni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
2024	—	`conf`	Onboard FPGA AI/ML Processing on Landsat-8 Satellite Images: A Case Study of Wildfires Detection. ApplePies Lorenzo Canese, Gian Carlo Cardarilli, Giuseppe D'Angelo, Luca Di Nunzio, Piero Gabellini, Riccardo La Cesa, Marco Re, Sergio Spanò
2023	Misc	`conf`	A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning. ACSSC Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
2023	—	`conf`	A RISC-V Hardware Accelerator for Q-Learning Algorithm. ApplePies Damiano Angeloni, Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Sergio Spanò
2023	J	`jnl`	An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò
2023	J	`jnl`	Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming. IEEE Trans. Circuits Syst. II Express Briefs Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Sergio Spanò
2023	Misc	`conf`	Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re
2022	—	`conf`	AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation. ApplePies D. Errico, Marco Re, V. Colombo, Gian Carlo Cardarilli, M. Martina, M. Ruo Roch
2022	J	`jnl`	An FPGA-based multi-agent Reinforcement Learning timing synchronizer. Comput. Electr. Eng. Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Andrea Ricci, Sergio Spanò
2022	—	`conf`	Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators. ApplePies Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
2022	J	`jnl`	Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re
2022	—	`conf`	FPGA-Based Road Crack Detection Using Deep Learning. SYSINT Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
2022	J	`jnl`	Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance. Sensors Lorenzo Canese, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Hamed Famil Ghadakchi, Marco Re, Sergio Spanò
2021	—	`conf`	"MR Q-Learning" Algorithm for Efficient Hardware Implementations. ACSCC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Dario Natale, Marco Re, Sergio Spanò
2021	—	`conf`	A M-PSK Timing Recovery Loop Based on Q-Learning. ApplePies Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Matteo Guadagno, Marco Re, Sergio Spanò
2021	J	`jnl`	A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic. IEEE Trans. Circuits Syst. II Express Briefs Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Massimo Panella, Marco Re, Antonello Rosato, Sergio Spanò
2021	—	`conf`	Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT. SYSTEM Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Marco Re
2021	J	`jnl`	M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
2020	J	`jnl`	AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps. IEEE Trans. Circuits Syst. II Express Briefs Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Sergio Spanò
2020	—	`conf`	An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators. ApplePies Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò
2020	Misc	`conf`	FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò
2020	J	`jnl`	N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
2019	J	`jnl`	A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò
2019	—	`conf`	Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning. ApplePies Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Sergio Spanò
2019	J	`jnl`	An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re
2019	Misc	`conf`	Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2019	—	`conf`	Digital Signal Processing Accelerator for RISC-V. ICECS L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2018	Misc	`conf`	A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2018	—	`conf`	Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming. ApplePies Gian Carlo Cardarilli, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Lorenzo Simone, Sergio Spanò
2018	—	`conf`	Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò
2018	—	`conf`	Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration. ApplePies Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò
2018	J	`jnl`	Hardware design of LIF with Latency neuron model with memristive STDP synapses. CoRR Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi
2018	—	`conf`	IP Generator Tool for Efficient Hardware Acceleration of Self-organizing Maps. ApplePies Daniele Giardino, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò
2018	—	`conf`	Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility. DTIS Marco Ottavi, Dario Asciolla, Tiziano Fiorucci, Elena Grosso, Carla Marzullo, Alessandro Scaramella, Simone Stramaccioni, Alessia Zibecchi, Carla Andreani, Gian Carlo Cardarilli, Carlo Cazzaniga, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Pedro Reviriego, Gianluca Furano, Roberto Senesi
2017	C	`conf`	A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements. ISCAS Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Luca Gerardi, Marco Re, Giovanni Campolo, Domenico Cascone
2017	—	`conf`	Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR. ApplePies Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Marco Matta, Marco Re, Francesca Silvestri, Sergio Spanò, Dario Gelfusa, Lorenzo Simone
2017	—	`conf`	FPGA Implementation of a Channelizer with 2048 Channels Utilizing USRP-SDR Platform for Satellite Communications. ApplePies Simone Acciarito, Daniele Giardino, Gaurav Mani Khanal, Marco Re, Francesca Silvestri, Sergio Spanò
2017	—	`conf`	FPGA Implementation of a Low-Power QRS Extractor. ApplePies Francesca Silvestri, Simone Acciarito, Gian Carlo Cardarilli, Gaurav Mani Khanal, Luca Di Nunzio, Rocco Fazzolari, Marco Re
2017	J	`jnl`	Hardware design of LIF with Latency neuron model with memristive STDP synapses. Integr. Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi
2017	—	`conf`	Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari
2016	—	`conf`	A hardware framework for on-chip FPGA acceleration. ISIC Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2016	—	`conf`	Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach. ApplePies Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re
2016	—	`conf`	Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams. DFT Filippo Giuliani, Marco Ottavi, Gian Carlo Cardarilli, Marco Re, Luca Di Nunzio, Rocco Fazzolari, Antimo Bruno, Francesco Zuliani
2016	Misc	`conf`	Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2016	—	`conf`	ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior. ApplePies Gaurav Mani Khanal, Simone Acciarito, Gian Carlo Cardarilli, Abhishek Chakraborty, Luca Di Nunzio, Rocco Fazzolari, Alessandro Cristini, Gianluca Susi, Marco Re
2015	—	`conf`	A Wireless Sensor Node Based on Microbial Fuel Cell. ApplePies Simone Acciarito, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
2015	—	`conf`	A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re
2015	—	`conf`	Characterization of RNS multiply-add units for power efficient DSP. MWSCAS Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2015	J	`jnl`	High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates. J. Electr. Comput. Eng. Amirhossein Fereidountabar, Gian Carlo Cardarilli, Marco Re
2014	—	`conf`	TDES cryptography algorithm acceleration using a reconfigurable functional unit. ICECS Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
2014	—	`conf`	Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2013	—	`conf`	A Reconfigurable Functional Unit for Modular Operations. ApplePies Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Salvatore Pontarelli, Marco Re
2013	Misc	`conf`	Compressive sensing spectrum analysis for space autonomous radio receivers. ACSSC Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone
2013	—	`conf`	High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs. ApplePies Gian Carlo Cardarilli, Marco Re, Ilir Shuli
2013	Misc	`conf`	Spiking neural networks based on LIF with latency: Simulation and synchronization effects. ACSSC Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Marco Re, Mario Salerno, Gianluca Susi
2013	Misc	`conf`	Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2012	—	`conf`	Imprecise arithmetic for low power image processing. ACSCC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2012	—	`conf`	Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving. ACSCC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re, Ruby B. Lee
2012	—	`conf`	Karatsuba implementation of FIR filters. ACSCC Pietro Albicocco, Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re
2012	J	`jnl`	Optimized Implementation of RNS FIR Filters Based on FPGAs. J. Signal Process. Syst. Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2012	—	`conf`	Power efficient design of parallel/serial FIR filters in RNS. ACSCC Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2011	—	`conf`	Fine-grain Reconfigurable Functional Unit for embedded processors. ACSCC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
2011	—	`conf`	Partial reconfiguration in the implementation of autonomous radio receivers for space. ReCoSoC Gian Carlo Cardarilli, Marco Re, Ilir Shuli, Lorenzo Simone
2010	—	`conf`	Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit. WISES Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Marco Re
2010	—	`conf`	VLSI implementation of reconfigurable cells for RFU in embedded processors. ICECS Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Christian Lenci, Marco Re
2009	C	`conf`	Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units. ISCAS Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
2009	—	`conf`	Error Correction Codes for SEU and SEFI Tolerant Memory Systems. DFT Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2009	C	`conf`	Error detection in addition chain based ECC Point Multiplication. IOLTS Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2009	C	`conf`	Improved Large-signal Model for Vacuum Triodes. ISCAS Gian Carlo Cardarilli, Marco Re, Leonardo Di Carlo
2009	C	`conf`	Speed-up of RISC Processor Computation using ADAPTO. ISCAS Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
2008	—	`conf`	A Novel Error Detection and Correction Technique for RNS Based FIR Filters. DFT Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2008	—	`conf`	A Software Defined Radio Architecture for a Regenerative Onboard processor. AHS Francesco Iacomacci, Catherine Morlet, Francesca Autelitano, Gian Carlo Cardarilli, Marco Re, Enrico Petrongari, Gino Bogo, Mario Franceschelli
2008	—	`conf`	A full-adder based reconfigurable architecture for fine grain applications: ADAPTO. ICECS Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re
2008	C	`conf`	ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli
2008	—	`conf`	On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2008	—	`conf`	On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs. ICECS Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2008	—	`conf`	Reducing power dissipation in pipelined accumulators. ACSCC Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2008	C	`conf`	Totally Fault Tolerant RNS Based FIR Filters. IOLTS Salvatore Pontarelli, Gian Carlo Cardarilli, Marco Re, Adelio Salsano
2007	J	`jnl`	Analysis of Errors and Erasures in Parity Sharing RS Codecs. IEEE Trans. Computers Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2007	J	`jnl`	Concurrent Error Detection in Reed-Solomon Encoders and Decoders. IEEE Trans. Very Large Scale Integr. Syst. Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2007	C	`conf`	Low-power adaptive filter based on RNS components. ISCAS G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2007	—	`conf`	Optimization of Self Checking FIR filters by means of Fault Injection Analysis. DFT Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2007	C	`conf`	Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. IOLTS Salvatore Pontarelli, Luca Sterpone, Gian Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante
2006	C	`conf`	Concurrent error detection in Reed Solomon decoders. ISCAS Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2006	J	`jnl`	Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders. IEEE Trans. Computers Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2006	C	`conf`	Fault tolerant design of signed digit based FIR filters. ISCAS Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2006	C	`conf`	Localization of Faults in Radix-n Signed Digit Adders. IOLTS Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2006	C	`conf`	Optimized QPSK modulator for DVB-S applications. ISCAS Gian Carlo Cardarilli, Andrea Del Re, Marco Re, Lorenzo Simone
2005	J	`jnl`	A Comparative Evaluation of Designs for Reliable Memory Systems. J. Electron. Test. Gian Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2005	—	`conf`	A Self Checking Reed Solomon Encoder: Design and Analysis. DFT Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2005	C	`conf`	Design of a Self Checking Reed Solomon Encoder. IOLTS Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2005	—	`conf`	FPGA implementation of a general purpose HMM processor based on token passing algorithm. ECCTD D. Bianchi, Gian Carlo Cardarilli, Andrea Del Re, A. Malatesta, Marco Re
2005	—	`conf`	FPGA oriented design of parity sharing RS codecs. DFT Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano
2005	—	`conf`	Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2004	C	`conf`	A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. IOLTS Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2004	A	`conf`	A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. DATE Andrea Del Re, Alberto Nannarelli, Marco Re
2004	—	`conf`	Data Integrity Evaluations of Reed Solomon Codes for Storage Systems. DFT Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2004	—	`conf`	Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2003	—	`conf`	A fault tolerant hardware based file system manager for solid state mass memory. ISCAS (5) Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2003	J	`jnl`	Design of a fault tolerant solid state mass memory. IEEE Trans. Reliab. Gian Carlo Cardarilli, A. Leandri, P. Marinucci, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2003	—	`conf`	Error Detection in Signed Digit Arithmetic Circuit with Parity Checker. DFT Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano
2003	—	`conf`	IP based reconfigurable digital platform for satellite communications. ISCAS (2) Gian Carlo Cardarilli, Andrea Del Re, Marco Re
2003	J	`jnl`	Perspectives of QoS Management Based on QoAS for 3G Communication Systems. Wirel. Pers. Commun. Roberto Lojacono, Marco Re, Maurizio Caciotta, Fabio Leccese, Dario Petri, Antonio Moschitta, Claudio Gennarelli, Giovanni Riccio, Pasquale Daponte, Sergio Rapuano, Domenico Grimaldi, Salvatore Graziani, Silvia Sangiovanni
2003	—	`conf`	Power-delay tradeoffs in residue number system. ISCAS (5) Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re
2002	—	`conf`	A self-checking cell logic block for fault tolerant FPGAs. ISCAS (4) Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano
2002	J	`jnl`	Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System. VLSI Design Marco Re, Andrea Del Re, Gian Carlo Cardarilli
2002	—	`conf`	Power characterization of digital filters implemented on FPGA. ISCAS (5) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2001	—	`conf`	Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines. DFT Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano
2001	—	`conf`	FPGA realization of RNS to binary signed conversion architecture. ISCAS (4) Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono
2001	—	`conf`	System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology. DFT Salvatore Pontarelli, Gian Carlo Cardarilli, A. Malvoni, Marco Ottavi, Marco Re, Adelio Salsano
2001	—	`conf`	Tradeoffs between residue number system and traditional FIR filters. ISCAS (2) Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli
2000	C	`conf`	A CAD environment for fuzzy systems HW/SW mapping. ISCAS Marco Re, Marcello Salmeri, Gian Carlo Cardarilli
2000	B	`conf`	A novel bacterial algorithm to extract the rule base from a training set. FUZZ-IEEE Marcello Salmeri, Marco Re, Enrico Petrongari, Gian Carlo Cardarilli
2000	C	`conf`	FPGA implementation of a demux based on a multirate filter bank. ISCAS Marco Re, Gian Carlo Cardarilli, Andrea Del Re, Roberto Lojacono
1999	—	`conf`	Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion. ISCAS (2) Alberto L. Sangiovanni-Vincentelli, Marco Re, Luciano Lavagno, Gian Carlo Cardarilli, Roberto Lojacono
1999	—	`conf`	Bipolar and CMOS low voltage-supply reduced-power voltage followers. ICECS Giuseppe Ferri, Franco Alfonsetti, Gian Carlo Cardarilli, Marco Re
1998	J	`jnl`	VLSI implementation of a real time fuzzy processor. J. Intell. Fuzzy Syst. Gian Carlo Cardarilli, Marco Re, Roberto Lojacono