Marco Mestice

13 papers Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2025 — conf
A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique.
NewCAS
Mohammadreza Esmaeilpour, Marco Mestice, Jan Lappas, Christian Weis, Norbert Wehn
2025 — conf
A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology.
SOCC
Marco Mestice, Johannes Feldmann, Jan Lappas, Mohammadreza Esmaeilpour, Christian Weis, Norbert Wehn
2025 J jnl
Modeling, Analysis, and Comparison of Voltage and Charge Sampling Techniques in Sub-Sampling PLL Design.
IEEE Access
Gabriele Ciarpi, Danilo Monda, Marco Mestice, Daniele Rossi, Sergio Saponara
2024 — conf
An Area-Oriented Approach to the System-Level Design of Charge-Pump Phase-Locked Loops.
ApplePies
Marco Mestice, Gabriele Ciarpi, Daniele Rossi, Sergio Saponara
2024 J jnl
Design and Experimental Verification of a 6.25-GHz PLL for Harsh Temperature Conditions in 65-nm CMOS Technology.
IEEE Trans. Instrum. Meas.
Marco Mestice, Gabriele Ciarpi, Daniele Rossi, Sergio Saponara
2023 — conf
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments.
ICECS
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Fabrizio Palla, Sergio Saponara
2023 J jnl
A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications.
IEEE Access
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Fabrizio Palla, Sergio Saponara
2023 — conf
Smart Kinetic Floor System for Energy Harvesting and Data Acquisition in High Foot-Traffic Areas.
ApplePies
Gabriele Ciarpi, Ettore Noccetti, Luca Ceragioli, Marco Mestice, Daniele Rossi, Sergio Saponara
2023 — conf
Wire Bonding: Limitations and Opportunities for High-Speed Serial Communications.
ApplePies
Gabriele Ciarpi, Marco Mestice, Daniele Rossi, Sergio Saponara
2022 — conf
A 2 GHz Wide Tuning Range LC-Tank Digitally Controlled Oscillator in 28 nm CMOS Technology.
ApplePies
Gabriele Ciarpi, G. Puccioni, Marco Mestice, Danilo Monda, Daniele Rossi, Sergio Saponara
2022 — conf
A Low-Area, Low-Power, Wide Tuning Range Digitally Controlled Oscillator for Power Management Systems in 28 nm CMOS Technology.
ApplePies
Marco Mestice, G. Biondi, Gabriele Ciarpi, Daniele Rossi, Sergio Saponara
2020 J jnl
Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL.
Sensors
Marco Mestice, Bruno Neri, Gabriele Ciarpi, Sergio Saponara
2019 — conf
Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard.
ApplePies
Marco Mestice, Bruno Neri, Sergio Saponara