Marco Lanuzza - RankMe

110 papers A* 1A 1B 1C 15Misc 1Journal 60Unranked 30

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Hardware-Aware Model Design and Training of Silicon-based Analog Neural Networks. CoRR Giulio Filippeschi, Mirko Brazzini, Cristhopher Mosquera, Marco Lanuzza, Alessandro Catania, Sebastiano Strangio, Giuseppe Iannaccone
2026	J	`jnl`	NV-PCAM: Non-Volatile Precharge-Free Content-Addressable Memory. IEEE Trans. Circuits Syst. I Regul. Pap. Oliver Caisaluisa, Esteban Garzón, Eduardo Holguín, Marco Lanuzza, Luis-Miguel Prócel
2026	J	`jnl`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CoRR Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2026	J	`jnl`	SPARCAM: Sparse matrix multiplication accelerator using multi-port dynamic CAM. J. Syst. Archit. Esteban Garzón, Benjamin Zambrano, David Sheinenzon, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance. IEEE J. Solid State Circuits Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	C	`conf`	A Multi-Bit PUF Architecture Using a 2T Sub-Threshold Voltage Divider. ISCAS Massimo Vatalaro, Raffaele De Rose, Vincenzo Maccaronio, Marco Lanuzza, Felice Crupi
2025	J	`jnl`	Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations. IEEE Trans. Circuits Syst. I Regul. Pap. Massimo Vatalaro, Raffaele De Rose, Vincenzo Maccaronio, Marco Lanuzza, Felice Crupi
2025	C	`conf`	Low Matchline Voltage Swing Content-Addressable Memory Cell. ISCAS Cristhopher Mosquera, Ramiro Taco, Benjamin Zambrano, Luis-Miguel Procel, Esteban Garzón, Marco Lanuzza
2025	C	`conf`	Non-Volatile Content-Addressable Memory For Energy-Efficient & High-Performance Search And Update Operations. ISCAS Alessandro Bedoya, Benjamin Zambrano, Ramiro Taco, Luis-Miguel Prócel, Marco Lanuzza, Esteban Garzón
2025	J	`jnl`	PUF-Based Authentication-Oriented Architecture for Identification Tags. IEEE Trans. Dependable Secur. Comput. Antonino Rullo, Carmelo Felicetti, Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Domenico Saccà
2025	—	`conf`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CCMCC Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	SpaceCAM: A 16 nm FinFET Low-Power Soft-Error Tolerant TCAM Design for Space Communication Applications. IEEE Access Itay Merlin, Benjamin Zambrano, Marco Lanuzza, Alexander Fish, Avner Haran, Leonid Yavits
2025	C	`conf`	Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. ISCAS Ramiro Taco, Esteban Garzón, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	Designing Precharge-Free Energy-Efficient Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. Ramiro Taco, Esteban Garzón, Robert Hanhan, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
2023	J	`jnl`	AM IEEE J. Emerg. Sel. Topics Circuits Syst. Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	Efficiency of Double-Barrier Magnetic Tunnel Junction-Based Digital eNVM Array for Neuro-Inspired Computing. IEEE Trans. Circuits Syst. II Express Briefs Tatiana Moposita, Esteban Garzón, Felice Crupi, Lionel Trojman, Andrei Vladimirescu, Marco Lanuzza
2023	J	`jnl`	Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access Hanan Marinberg, Esteban Garzón, Tzachi Noy, Marco Lanuzza, Adam Teman
2023	J	`jnl`	SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing. IEEE Access Tatiana Moposita, Esteban Garzón, Raffaele De Rose, Felice Crupi, Andrei Vladimirescu, Lionel Trojman, Marco Lanuzza
2023	—	`conf`	STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
2023	J	`jnl`	Voltage Reference With Corner-Aware Replica Selection/Merging for 1.4-mV Accuracy in Harvested Systems Down to 3.9 pW, 0.2 V. IEEE Access Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2023	J	`jnl`	XNOR-Bitcount Operation Exploiting Computing-In-Memory With STT-MRAMs. IEEE Trans. Circuits Syst. II Express Briefs Ariana Musello, Esteban Garzón, Marco Lanuzza, Luis-Miguel Prócel, Ramiro Taco
2022	J	`jnl`	A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Felice Crupi, Marco Lanuzza
2022	J	`jnl`	A 0.6V$-$1.8V Compact Temperature Sensor with 0.24°C Resolution, $\pm$1.4°C Inaccuracy and 1.06nJ per Conversion. CoRR Benjamin Zambrano, Esteban Garzón, Sebastiano Strangio, Giuseppe Iannaccone, Marco Lanuzza
2022	C	`conf`	A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman
2022	J	`jnl`	AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	J	`jnl`	Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza
2022	J	`jnl`	All-Analog Silicon Integration of Image Sensor and Neural Computing Engine for Image Classification. IEEE Access Benjamin Zambrano, Sebastiano Strangio, Tommaso Rizzo, Esteban Garzón, Marco Lanuzza, Giuseppe Iannaccone
2022	A*	`conf`	EDAM: edit distance tolerant approximate matching content addressable memory. ISCA Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2022	J	`jnl`	Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing. CoRR Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza
2022	—	`conf`	Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider. ICECS 2022 Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi
2022	J	`jnl`	Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm. IEEE J. Solid State Circuits Massimo Vatalaro, Raffaele De Rose, Marco Lanuzza, Felice Crupi
2022	—	`conf`	Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories. LASCAS Esteban Garzón, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza
2022	—	`conf`	Voltage-to-Voltage Sigmoid Neuron Activation Function Design for Artificial Neural Networks. LASCAS Tatiana Moposita, Lionel Trojman, Felice Crupi, Marco Lanuzza, Andrei Vladimirescu
2021	J	`jnl`	A 0.6-to-1.8V CMOS Current Reference With Near-100% Power Utilization. IEEE Trans. Circuits Syst. II Express Briefs Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021	—	`conf`	A 3.2-pW, 0.2-V Trimming-Less Voltage Reference with 1.4-mV Across-Wafer Total Accuracy. ESSCIRC Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021	J	`jnl`	A Robust, High-Speed and Energy-Efficient Ultralow-Voltage Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs Luigi Fassio, Francesco Settino, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2021	—	`conf`	Exploiting Silicon Fingerprint for Device Authentication Using CMOS-PUF and ECC. SmartIoT Carmelo Felicetti, Marco Lanuzza, Antonino Rullo, Domenico Saccà, Felice Crupi
2021	J	`jnl`	Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman
2021	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2021	—	`conf`	High-Speed and Low-Energy Dual-Mode Logic based Single-Clack-Cycle Binary Comparator. LASCAS Ricardo Escobar, Luis-Miguel Prócel, Lionel Trojman, Marco Lanuzza, Ramiro Taco
2021	C	`conf`	Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. ISCAS Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
2021	C	`conf`	Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. ISCAS Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish
2021	—	`conf`	RF-DC Multiplier for RF Energy Harvester based on 32nm and TFET technologies. LASCAS Lionel Trojman, David Rivadeneira, Marco Villegas, Eliana Acurio, Marco Lanuzza, Luis-Miguel Procel, Ramiro Taco
2021	J	`jnl`	Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW. IEEE J. Solid State Circuits Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2020	—	`conf`	A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm VLSI Circuits Luigi Fassio, Longyang Lin, Raffaele De Rose, Marco Lanuzza, Felice Crupi, Massimo Alioto
2020	J	`jnl`	Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework. Integr. Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza
2020	C	`conf`	Exploiting Single-Well Design for Energy-Efficient Ultra-Wide Voltage Range Dual Mode Logic-Based Digital Circuits in 28nm FD-SOI Technology. ISCAS Ramiro Taco, Leonid Yavits, Netanel Shavit, Inbal Stanger, Marco Lanuzza, Alexander Fish
2020	C	`conf`	Robust Dual Mode Pass Logic (DMPL) for Energy Efficiency and High Performance. ISCAS Inbal Stanger, Netanel Shavit, Ramiro Taco, Leonid Yavits, Marco Lanuzza, Alexander Fish
2020	J	`jnl`	Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. IEEE Trans. Circuits Syst. II Express Briefs Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish
2019	J	`jnl`	An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI. IEEE J. Solid State Circuits Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2019	—	`conf`	An Energy Aware Variation-Tolerant Writing Termination Control for STT-based Non Volatile Flip-Flops. ICECS Marco Lanuzza, Raffaele De Rose, Felice Crupi, Massimo Alioto
2019	—	`conf`	Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory. ICECS Esteban Garzón, Raffaele De Rose, Felice Crupi, Marco Lanuzza
2019	J	`jnl`	Double-precision Dual Mode Logic carry-save multiplier. Integr. Raffaele De Rose, Paul Romero, Marco Lanuzza
2019	—	`conf`	Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers. ASICON Marco Lanuzza, Raffaele De Rose, Esteban Garzón, Felice Crupi
2019	—	`conf`	Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs. SMACD Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Giovanni Finocchio, Mario Carpentieri, Marco Lanuzza
2019	C	`conf`	Live Demo: An 88fJ / 40 MHz [0.4V] - 0.61pJ / 1GHz [0.9V] Dual Mode Logic 8×8-Bit Multiplier Accumulator with a Self-Adjustment Mechanism in 28 nm FD-SOI. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2019	—	`conf`	Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions. IDCS Carmelo Felicetti, Angelo Furfaro, Domenico Saccà, Massimo Vatalaro, Marco Lanuzza, Felice Crupi
2018	J	`jnl`	A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
2018	J	`jnl`	A portable class of 3-transistor current references with low-power sub-0.5 V operation. Int. J. Circuit Theory Appl. Felice Crupi, Raffaele De Rose, Maksym Paliy, Marco Lanuzza, Mattia Perna, Giuseppe Iannaccone
2018	—	`conf`	Design of a 3T current reference for low-voltage, low-power operation. ICICDT Raffaele De Rose, Felice Crupi, Maksym Paliy, Marco Lanuzza, Giuseppe Iannaccone
2018	—	`conf`	Impact of the Emitter Contact Pattern in c-Si BC- BJ Solar Cells by Numerical Simulations. RTSI Noemi Guerra, Raffaele De Rose, Marco Guevara, Paul Procel, Marco Lanuzza, Felice Crupi
2017	J	`jnl`	A physical unclonable function based on a 2-transistor subthreshold voltage divider. Int. J. Circuit Theory Appl. Raffaele De Rose, Felice Crupi, Marco Lanuzza, Domenico Albano
2017	C	`conf`	A variation-aware simulation framework for hybrid CMOS/spintronic circuits. ISCAS Raffaele De Rose, Marco Lanuzza, Felice Crupi, Giulio Siracusano, Riccardo Tomasello, Giovanni Finocchio, Mario Carpentieri, Massimo Alioto
2017	J	`jnl`	An Ultralow-Voltage Energy-Efficient Level Shifter. IEEE Trans. Circuits Syst. II Express Briefs Marco Lanuzza, Felice Crupi, Sandro Rao, Raffaele De Rose, Sebastiano Strangio, Giuseppe Iannaccone
2017	—	`conf`	Design of a sub-1-V nanopower CMOS current reference. ECCTD Raffaele De Rose, Domenico Albano, Felice Crupi, Marco Lanuzza
2017	C	`conf`	Evaluation of Dual Mode Logic in 28nm FD-SOI technology. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2017	—	`conf`	Impact of voltage scaling on STT-MRAMs through a variability-aware simulation framework. SMACD Raffaele De Rose, Greta Carangelo, Marco Lanuzza, Felice Crupi, Giovanni Finocchio, Mario Carpentieri
2017	J	`jnl`	Low energy/delay overhead level shifter for wide-range voltage conversion. Int. J. Circuit Theory Appl. Marco Lanuzza, Felice Crupi, Sandro Rao, Raffaele De Rose, Giuseppe Iannaccone
2016	C	`conf`	Extended exploration of low granularity back biasing control in 28nm UTBB FD-SOI technology. ISCAS Ramiro Taco, Itamar Levi, Marco Lanuzza, Alexander Fish
2015	J	`jnl`	Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs. IEEE Trans. Very Large Scale Integr. Syst. Marco Lanuzza, Pasquale Corsonello, Stefania Perri
2015	J	`jnl`	Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int. J. Circuit Theory Appl. Domenico Albano, Marco Lanuzza, Ramiro Taco, Felice Crupi
2015	J	`jnl`	Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits. VLSI Design Ramiro Taco, Marco Lanuzza, Domenico Albano
2014	J	`jnl`	Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int. J. Circuit Theory Appl. Fabio Frustaci, Marco Lanuzza, Stefania Perri, Pasquale Corsonello
2014	J	`jnl`	Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. Int. J. Circuit Theory Appl. Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2014	J	`jnl`	Designing Dynamic Carry Skip Adders: Analysis and Comparison. Circuits Syst. Signal Process. Raffaele De Rose, Marco Lanuzza, Fabio Frustaci, Sohan Purohit
2014	—	`conf`	Dynamic gate-level body biasing for subthreshold digital design. LASCAS Marco Lanuzza, Ramiro Taco, Domenico Albano
2014	J	`jnl`	Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. Pasquale Corsonello, Marco Lanuzza, Stefania Perri
2014	—	`conf`	Improving speed and power characteristics of pulse-triggered flip-flops. LASCAS Marco Lanuzza, Ramiro Taco
2014	J	`jnl`	Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain. IEEE Trans. Circuits Syst. I Regul. Pap. Pasquale Corsonello, Fabio Frustaci, Marco Lanuzza, Stefania Perri
2013	J	`jnl`	A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops. J. Low Power Electron. Marco Lanuzza
2012	J	`jnl`	Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2012	J	`jnl`	Energy-efficient single-clock-cycle binary comparator. Int. J. Circuit Theory Appl. Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2012	J	`jnl`	Low-Power Level Shifter for Multi-Supply Voltage Designs. IEEE Trans. Circuits Syst. II Express Briefs Marco Lanuzza, Pasquale Corsonello, Stefania Perri
2010	C	`conf`	A new low-power high-speed single-clock-cycle binary comparator. ISCAS Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello
2010	J	`jnl`	Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. J. Low Power Electron. Sohan Purohit, Marco Lanuzza, Martin Margala
2010	J	`jnl`	Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications. ACM Trans. Reconfigurable Technol. Syst. Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. ISVLSI Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis. PATMOS Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2010	—	`conf`	Impact of Random Process Variations on Different 65nm SRAM Cell Topologies. ICETET Sumit Kansal, Marco Lanuzza, Pasquale Corsonello
2009	—	`conf`	A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. PATMOS Fabio Frustaci, Marco Lanuzza
2009	—	`conf`	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications. ARC Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. J. Low Power Electron. Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	Misc	`conf`	Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. VLSI Design Sohan Purohit, Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2009	J	`jnl`	Designing High-Speed Adders in Power-Constrained Environments. IEEE Trans. Circuits Syst. II Express Briefs Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2009	J	`jnl`	Low-power split-path data-driven dynamic logic. IET Circuits Devices Syst. Fabio Frustaci, Marco Lanuzza, Paolo Zicari, Stefania Perri, Pasquale Corsonello
2009	—	`conf`	New performance/power/area efficient, reliable full adder design. ACM Great Lakes Symposium on VLSI Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello
2008	—	`conf`	Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing. PATMOS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2007	—	`conf`	A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications. AHS Marco Lanuzza, Stefania Perri, Pasquale Corsonello, Martin Margala
2007	C	`conf`	Design and Implementation of a 90nm Low bit-rate Image Compression Core. DSD Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
2007	—	`conf`	MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing. SAMOS Marco Lanuzza, Stefania Perri, Pasquale Corsonello
2006	J	`jnl`	Low bit rate image compression core for onboard space applications. IEEE Trans. Circuits Syst. Video Technol. Pasquale Corsonello, Stefania Perri, Giovanni Staino, Marco Lanuzza, Giuseppe Cocorullo
2005	J	`jnl`	A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsystems Stefania Perri, Marco Lanuzza, Pasquale Corsonello, Giuseppe Cocorullo
2005	A	`conf`	Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applications. ISLPED Marco Lanuzza, Martin Margala, Pasquale Corsonello
2005	B	`conf`	Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. FPL Marco Lanuzza, Stefania Perri, Martin Margala, Pasquale Corsonello
2005	—	`—`	Progetto e realizzazione VLSI di circuiti aritmetici ottimizzati per applicazioni multimediali. Marco Lanuzza
2004	J	`jnl`	Variable precision arithmetic circuits for FPGA-based multimedia processors. IEEE Trans. Very Large Scale Integr. Syst. Stefania Perri, Pasquale Corsonello, Maria Antonia Iachino, Marco Lanuzza, Giuseppe Cocorullo