Marcin Rogawski

19 papers A 3B 3C 1Journal 9Unranked 3
YearRankTypeTitle / Venue / Authors
2016 B conf
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off.
FPL
Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski
2014 B conf
A novel modular adder for one thousand bits and more using fast carry chains of modern FPGAs.
FPL
Marcin Rogawski, Ekawat Homsirikamol, Kris Gaj
2014 A conf
ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption.
CHES
Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik
2014 J jnl
ICEPOLE: High-speed, Hardware-oriented Authenticated Encryption.
IACR Cryptol. ePrint Arch.
Pawel Morawiecki, Kris Gaj, Ekawat Homsirikamol, Krystian Matusiewicz, Josef Pieprzyk, Marcin Rogawski, Marian Srebrny, Marcin Wójcik
2013 J jnl
A high-speed unified hardware architecture for 128 and 256-bit security levels of AES and the SHA-3 candidate Grøstl.
Microprocess. Microsystems
Marcin Rogawski, Kris Gaj, Ekawat Homsirikamol
2012 C conf
A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate Grøstl.
DSD
Marcin Rogawski, Kris Gaj
2012 J jnl
Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs.
IACR Cryptol. ePrint Arch.
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid, Malik Umar Sharif
2012 — conf
Security Margin Evaluation of SHA-3 Contest Finalists through SAT-Based Attacks.
CISIM
Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny
2012 J jnl
Security margin evaluation of SHA-3 contest finalists through SAT-based attacks.
IACR Cryptol. ePrint Arch.
Ekawat Homsirikamol, Pawel Morawiecki, Marcin Rogawski, Marian Srebrny
2011 — conf
Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAs.
ReConFig
Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps
2011 J jnl
Groestl Tweaks and their Effect on FPGA Results.
IACR Cryptol. ePrint Arch.
Marcin Rogawski, Kris Gaj
2011 A conf
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs.
CHES
Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj
2011 — conf
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates.
FPT
Rabia Shahid, Malik Umar Sharif, Marcin Rogawski, Kris Gaj
2010 B conf
ATHENa - Automated Tool for Hardware EvaluatioN: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs.
FPL
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, Benjamin Y. Brewster
2010 J jnl
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve.
IEEE Trans. Computers
Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi, Marcin Rogawski
2010 J jnl
Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.
IACR Cryptol. ePrint Arch.
Ekawat Homsirikamol, Marcin Rogawski, Kris Gaj
2010 A conf
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.
CHES
Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski
2003 J jnl
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices
CoRR
Marcin Rogawski
2003 J jnl
Analysis of Implementation Hierocrypt-3 algorithm (and its comparison to Camellia algorithm) using ALTERA devices.
IACR Cryptol. ePrint Arch.
Marcin Rogawski