| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
Theory Pract. Log. Program.
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
Algorithms
|
| 2024 | J | jnl |
J. Heuristics
|
| 2023 | J | jnl |
CoRR
|
| 2020 | J | jnl |
Algorithms
|
| 2019 | J | jnl |
Algorithms
|
| 2019 | — | conf |
DEXA Workshops
|
| 2018 | A | conf |
A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices.
DATE
|
| 2018 | — | conf |
DEXA Workshops
|
| 2016 | J | jnl |
IEEE Trans. Computers
|
| 2015 | J | jnl |
Central Eur. J. Oper. Res.
|
| 2014 | J | jnl |
J. Electron. Test.
|
| 2014 | J | jnl |
IET Comput. Digit. Tech.
|
| 2009 | J | jnl |
J. Electron. Test.
|
| 2007 | — | conf |
DFT
|
| 2005 | — | conf |
Comparative Genomics
|
| 2002 | A | conf |
DATE
|
| 2002 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2002 | J | jnl |
IEEE Des. Test Comput.
|
| 2000 | A* | conf |
DAC
|
| 2000 | A | conf |
DATE
|
| 1999 | A | conf |
DATE
|
| 1999 | A* | conf |
DAC
|
| 1998 | J | jnl |
J. Electron. Test.
|
| 1997 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 1997 | J | jnl |
J. Electron. Test.
|
| 1996 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 1996 | A | conf |
ITC
|
| 1995 | — | conf |
ED&TC
|
| 1995 | Misc | conf |
VTS
|
| 1994 | — | conf |
EDAC-ETC-EUROASIC
|
| 1993 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 1993 | A | conf |
ITC
|
| 1993 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 1992 | A | conf |
ITC
|
| 1992 | A | conf |
ITC
|