Marcel A. Kossel

79 papers C 2Journal 29Unranked 48

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET. IEEE J. Solid State Circuits Jaewon Lee, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Yujin Choi, DongGeon Kim, Taekwang Jang, Gain Kim
2025	—	`conf`	7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET. ISSCC Jaewon Lee, Pier Andrea Francese, Matthias Brändli, Thomas Morf, Marcel A. Kossel, Seoyoung Jang, Gain Kim
2025	J	`jnl`	A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform. IEEE Trans. Very Large Scale Integr. Syst. Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	J	`jnl`	A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform. IEEE Trans. Circuits Syst. II Express Briefs Jaewon Lee, Seoyoung Jang, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	C	`conf`	A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. ISCAS Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Matthias Braendli, Marcel A. Kossel, Andrea Ruffino, Thomas Morf, Pier Andrea Francese, Gain Kim
2024	J	`jnl`	A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform. IEEE Trans. Circuits Syst. II Express Briefs Jaewon Lee, Seoyoung Jang, Yujin Choi, DongGeon Kim, Serdar A. Yonar, Matthias Braendli, Andrea Ruffino, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	J	`jnl`	A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC. IEEE Trans. Circuits Syst. II Express Briefs Jaewon Lee, Seoyoung Jang, DongGeon Kim, Yujin Choi, Jong-Hyeok Yoon, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	J	`jnl`	A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. DongGeon Kim, Yujin Choi, Jaewon Lee, Seoyoung Jang, Sungyu Song, Matthias Braendli, Thomas Morf, Marcel A. Kossel, Pier Andrea Francese, Gain Kim
2024	—	`conf`	Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli
2023	J	`jnl`	A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Troy J. Beukema, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2023	—	`conf`	An 8b 1.0-to-1.25GS/s 0.7-to-0.8V Single-Stage Time-Based Gated-Ring-Oscillator ADC with $2\times$ Interpolating Sense-Amplifier-Latches. ISSCC Serdar A. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Mridula Prathapan, Thomas Morf, Andrea Ruffino, Taekwang Jang
2023	J	`jnl`	Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs Sandro Widmer, Marcel A. Kossel, Giovanni Cherubini, Stanislaw Wozniak, Pier Andrea Francese, Ana Stanojevic, Matthias Brändli, Klaus Frick, Angeliki Pantazi
2022	—	`conf`	A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese, Matthias Brändli, Troy J. Beukema, Christian W. Baks, Jonathan E. Proesel, John F. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2022	—	`conf`	A cryogenic SRAM based arbitrary waveform generator in 14 nm for spin qubit control. ESSCIRC Mridula Prathapan, Peter Mueller, Christian Menolfi, Matthias Brändli, Marcel A. Kossel, Pier Andrea Francese, David Heim, Maria Vittoria Oropallo, Andrea Ruffino, Cezar B. Zota, Thomas Morf
2022	J	`jnl`	A system design approach toward integrated cryogenic quantum control systems. CoRR Mridula Prathapan, Peter Mueller, David Heim, Maria Vittoria Oropallo, Matthias Braendli, Pier Andrea Francese, Marcel A. Kossel, Andrea Ruffino, Cezar B. Zota, Eunjung Cha, Thomas Morf
2022	—	`conf`	An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits Serdar S. Yonar, Pier Andrea Francese, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin
2021	—	`conf`	An 8b DAC-Based SST TX Using Metal Gate Resistors with 1.4pJ/b Efficiency at 112Gb/s PAM-4 and 8-Tap FFE in 7iim CMOS. ISSCC Marcel A. Kossel, Vishal Khatri, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Serdar A. Yonar, Mridula Prathapan, Eric J. Lukes, Raymond A. Richetta, Carrie Cox
2021	—	`conf`	Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSCIRC Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota
2021	—	`conf`	Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology. ESSDERC Asma Chabane, Mridula Prathapan, Peter Mueller, Eunjung Cha, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf, Cezar B. Zota
2020	J	`jnl`	A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. IEEE J. Solid State Circuits Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf
2020	—	`conf`	A 25×50Gb/s 2.22pJ/b NRZ RX with Dual-Bank and 3-Tap Speculative DFE for Microprocessor Application in 7nm FinFET CMOS. VLSI Circuits Yang You, Glen A. Wiedemeier, Chad Marquart, Chris Steffen, Erik English, Dereje Yilma, Thomas Pham, Venkat Nammi, Jeffrey Okyere, Nathan Blanchard, Akil Sutton, Ze Zhang, David Friend, Diego Barba, Tyler Bohlke, Michael Spear, Vikram Raj, James Crugnale, Daniel Dreps, Pier Andrea Francese, Marcel A. Kossel, Thomas Morf
2019	—	`conf`	A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET. ISSCC Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl
2019	—	`conf`	A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET. ISSCC Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2019	—	`conf`	A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET. A-SSCC Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici
2018	—	`conf`	A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. VLSI Circuits Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya
2018	—	`conf`	A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. VLSI Circuits Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese, Matthias Braendli, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
2018	—	`conf`	A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS. ISSCC Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Alessandro Cevrero, Marcel A. Kossel, Lukas Kull, Danny Luu, Ilter Özkaya, Thomas Toifl
2018	J	`jnl`	A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang
2018	J	`jnl`	A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
2018	—	`conf`	A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET. ISSCC Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
2018	—	`conf`	A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. VLSI Circuits Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl
2018	—	`conf`	A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS. ISSCC Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Thomas Morf, Daniel M. Kuchta, Lukas Kull, Marcel A. Kossel, Danny Luu, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2018	J	`jnl`	A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2018	J	`jnl`	An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels. IEEE J. Solid State Circuits Cosimo Aprile, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
2018	J	`jnl`	Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
2018	C	`conf`	Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. ISCAS Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl, Yusuf Leblebici
2017	—	`conf`	28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. ISSCC Lukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl
2017	—	`conf`	29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET. ISSCC Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2017	J	`jnl`	A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET. IEEE J. Solid State Circuits Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl
2017	—	`conf`	Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET. ESSCIRC Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang
2017	—	`conf`	DDR4 transmitter with AC-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS technology. ESSCIRC Marcel A. Kossel, Christian Menolfi, Pier Andrea Francese, Lukas Kull, Thomas Morf, Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Danny Luu, Ilter Özkaya, Hazar Yueksel
2016	—	`conf`	23.6 A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path. ISSCC Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Alessandro Cevrero, Hazar Yueksel, Ilter Oezkaya, Danny Luu, Thomas Toifl
2016	—	`conf`	A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS. ESSCIRC Hazar Yueksel, Matthias Braendli, Andreas Burg, Giovanni Cherubini, Roy D. Cideciyan, Pier Andrea Francese, Simeon Furrer, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Thomas Toifl
2016	—	`conf`	Design considerations for 50G+ backplane links. ESSCIRC Thomas Toifl, Matthias Braendli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Ilter Özkaya, Hazar Yueksel
2016	J	`jnl`	Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS. IEEE J. Solid State Circuits Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2015	—	`conf`	10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ISSCC Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu
2015	—	`conf`	20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS. ISSCC Toke Meyer Andersen, Florian Krismer, Johann Walter Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Pier Andrea Francese
2015	—	`conf`	A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. ESSCIRC Hazar Yueksel, Lukas Kull, Andreas Burg, Matthias Braendli, Peter Buchmann, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Danny Luu, Thomas Toifl
2015	—	`conf`	A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS. VLSIC Alessandro Cevrero, Cosimo Aprile, Pier Andrea Francese, Urs Bapst, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Lukas Kull, Hazar Yueksel, Ilter Oezkaya, Yusuf Leblebici, Volkan Cevher, Thomas Toifl
2014	—	`conf`	22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS. ISSCC Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2014	—	`conf`	4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm ISSCC Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese
2014	—	`conf`	A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm A-SSCC Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2014	J	`jnl`	A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. IEEE J. Solid State Circuits Pier Andrea Francese, Thomas Toifl, Peter Buchmann, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen
2014	—	`conf`	A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. ESSCIRC Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Peter Buchmann, Thomas Morf, Marcel A. Kossel, Christian Menolfi, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel
2014	—	`conf`	A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. ESSCIRC Thomas Toifl, Peter Buchmann, Troy J. Beukema, Michael P. Beakes, Matthias Braendli, Pier Andrea Francese, Christian Menolfi, Marcel A. Kossel, Lukas Kull, Thomas Morf
2014	—	`conf`	A DDR3/4 memory link TX supporting 24-40 Ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI. ESSCIRC Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel
2013	J	`jnl`	A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. IEEE J. Solid State Circuits Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
2013	J	`jnl`	A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS. IEEE J. Solid State Circuits Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2013	—	`conf`	A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS. ISSCC Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici
2013	—	`conf`	A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. ISSCC Marcel A. Kossel, Christian Menolfi, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
2013	—	`conf`	An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. ISSCC Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf
2012	J	`jnl`	A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. IEEE J. Solid State Circuits Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Daniel Dreps, Troy J. Beukema, Andrea Prati, Daniele Gardellini, Marcel A. Kossel, Peter Buchmann, Matthias Braendli, Pier Andrea Francese, Thomas Morf
2012	J	`jnl`	A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman
2012	—	`conf`	A 28Gb/s source-series terminated TX in 32nm CMOS SOI. ISSCC Christian Menolfi, Juergen Hertle, Thomas Toifl, Thomas Morf, Daniele Gardellini, Matthias Braendli, Peter Buchmann, Marcel A. Kossel
2012	—	`conf`	A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Peter Buchmann, Pier Andrea Francese, Thomas Morf
2011	—	`conf`	A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. ISSCC Christian Menolfi, Thomas Toifl, Michael Ruegg, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Morf
2011	—	`conf`	A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu
2009	J	`jnl`	A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. IEEE J. Solid State Circuits Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Martin L. Schmatz
2009	—	`conf`	Design and phase noise analysis of a multiphase 6 to 11 GHz PLL. ESSCIRC George von Büren, David Barras, Heinz Jäckel, Alex Huber, Christian Kromer, Marcel A. Kossel
2009	J	`jnl`	LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. IEEE J. Solid State Circuits Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Peter Buchmann, Christian Menolfi, Thomas Toifl, Martin L. Schmatz
2008	J	`jnl`	A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. IEEE J. Solid State Circuits Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz
2008	—	`conf`	A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. ISSCC Marcel A. Kossel, Christian Menolfi, Jonas R. M. Weiss, Peter Buchmann, George von Büren, Lucio Rodoni, Thomas Morf, Thomas Toifl, Martin L. Schmatz
2007	—	`conf`	A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. ISSCC Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
2007	—	`conf`	A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. ISSCC Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
2006	J	`jnl`	A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. IEEE J. Solid State Circuits Thomas Toifl, Christian Menolfi, Michael Ruegg, Robert Reutemann, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz
2006	—	`conf`	A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement. ISSCC Jonas R. M. Weiss, Marcel A. Kossel, Christian Menolfi, Thomas Morf, Martin L. Schmatz, Thomas Toifl, Heinz Jäckel
2005	J	`jnl`	A 0.94-ps-RMS-jitter 0.016-mm IEEE J. Solid State Circuits Thomas Toifl, Christian Menolfi, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin L. Schmatz, Jonas R. M. Weiss
2004	J	`jnl`	Jitter Measurements of High-Speed Serial Links. IEEE Des. Test Comput. Marcel A. Kossel, Martin L. Schmatz
2004	J	`jnl`	Traceable correction method for complex reflection coefficient using calculable air line impedance standards. IEEE Trans. Instrum. Meas. Marcel A. Kossel, Pascal Leuchtmann, Jürg Rüfenacht