Marc Renaudin - RankMe

106 papers A* 1A 9B 5C 21Misc 2Journal 21Unranked 47

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks. MARS Radu Mateescu, Wendelin Serwe, Aymane Bouzafour, Marc Renaudin
2018	J	`jnl`	A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. J. Low Power Electron. Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson
2018	—	`conf`	Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits. ASYNC Aymane Bouzafour, Marc Renaudin, Hubert Garavel, Radu Mateescu, Wendelin Serwe
2014	J	`jnl`	Adaptive rate filtering a computationally efficient signal processing approach. Signal Process. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2014	—	`conf`	Clockless Design Performance Monitoring for Nanometer Technologies. ASYNC Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels
2013	A	`conf`	Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools. DATE Alex Yakovlev, Pascal Vivet, Marc Renaudin
2013	—	`conf`	Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. ASYNC Eslam Yahya, Laurent Fesquet, Yehea I. Ismail, Marc Renaudin
2012	—	`conf`	Tiempo Asynchronous Circuits System Verilog Modeling Language. ASYNC Marc Renaudin, Alain Fonkoua
2011	J	`jnl`	40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications. ACM Trans. Design Autom. Electr. Syst. Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard
2011	J	`jnl`	A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback CoRR Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2011	J	`jnl`	Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin
2010	—	`conf`	ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems. PATMOS Marc Renaudin
2010	J	`jnl`	Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies. Microelectron. Reliab. Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
2010	—	`conf`	Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
2010	C	`conf`	Evaluating transient-fault effects on traditional C-element's implementations. IOLTS Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
2010	B	`conf`	Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin
2009	A	`conf`	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard
2009	J	`jnl`	Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. EURASIP J. Adv. Signal Process. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2009	Misc	`conf`	Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin
2009	C	`conf`	Comparing transient-fault effects on synchronous and on asynchronous circuits. IOLTS Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis
2009	J	`jnl`	Constrained Asynchronous Ring Structures for Robust Digital Oscillators. IEEE Trans. Very Large Scale Integr. Syst. Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
2009	—	`conf`	Programmable/Stoppable Oscillator Based on Self-Timed Rings. ASYNC Eslam Yahya, Oussama Elissati, Hatem M. Zakaria, Laurent Fesquet, Marc Renaudin
2008	J	`jnl`	An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. J. Electr. Comput. Eng. Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2008	—	`conf`	Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm. ICECS Eslam Yahya, Marc Renaudin
2008	C	`conf`	Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle
2008	—	`conf`	High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. ASYNC Jérémie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin
2008	—	`conf`	Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin
2007	—	`conf`	A Novel Asynchronous e-FPGA Architecture for Security Applications. FPT Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst
2007	—	`conf`	A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS Sylvain Miermont, Pascal Vivet, Marc Renaudin
2007	C	`conf`	A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC Julien Goulier, Eric André, Marc Renaudin
2007	—	`conf`	A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC (Selected Papers) Julien Goulier, Eric André, Marc Renaudin
2007	—	`conf`	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet
2007	—	`conf`	Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. ICASSP (3) Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2007	—	`conf`	An on-pixel FPN reduction method for a high dynamic range CMO S imager. ESSCIRC Estelle Labonne, Gilles Sicard, Marc Renaudin
2007	—	`conf`	Computationally efficient adaptive rate sampling and filtering. EUSIPCO Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2007	J	`jnl`	DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
2007	J	`jnl`	Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Tech. Sci. Informatiques J. Fragoso, Gilles Sicard, Marc Renaudin
2007	J	`jnl`	FPGA Architecture for Multi-Style Asynchronous Logic CoRR N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
2007	C	`conf`	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2007	J	`jnl`	Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distributed Syst. Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon
2007	—	`conf`	Performance Modeling and Analysis of Asynchronous Linear-Pipeline with Time Variable Delays. ICECS Eslam Yahya, Marc Renaudin
2007	B	`conf`	The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois
2007	C	`conf`	Timed Asynchronous Circuits Modeling using SystemC. FDL Cedric Koch-Hofer, Marc Renaudin
2006	—	`conf`	A 100dB dynamic range CMOS image sensor with global shutter. ICECS Estelle Labonne, Gilles Sicard, Marc Renaudin, Pierre-Damien Berger
2006	—	`conf`	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin
2006	C	`conf`	Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS Marc Renaudin, Yannick Monnet
2006	C	`conf`	Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel
2006	J	`jnl`	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers Yannick Monnet, Marc Renaudin, Régis Leveugle
2006	J	`jnl`	On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electron. David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin
2006	A	`conf`	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
2006	C	`conf`	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet
2006	—	`conf`	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS Eslam Yahya, Marc Renaudin
2006	C	`conf`	Security evaluation of dual rail logic against DPA attacks. VLSI-SoC Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin
2006	—	`conf`	Spectral analysis of a signal driven sampling scheme. EUSIPCO Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin
2006	C	`conf`	State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC Laurent Fesquet, Bertrand Folco, Mathieu Steiner, Marc Renaudin
2005	A	`conf`	A 120nm low power asynchronous ADC. ISLPED Emmanuel Allier, Julien Goulier, Gilles Sicard, Alessandro Dezzani, Eric André, Marc Renaudin
2005	—	`conf`	A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine
2005	B	`conf`	A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL Laurent Fesquet, Marc Renaudin
2005	—	`conf`	A clock-less low-voltage AES crypto-processor. ESSCIRC G. Fraidy Bouesse, Marc Renaudin, Adrien Witon, Fabien Germain
2005	—	`conf`	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin
2005	—	`conf`	Asynchrnous Architecture for Sensor Network Nodes. Med-Hoc-Net Aurélien Buhrig, Marc Renaudin, Dominique Barthel
2005	—	`conf`	Asynchronous Systems on Programmable Logic. ReCoSoC Laurent Fesquet, Jerome Quartana, Marc Renaudin
2005	A*	`conf`	Asynchronous circuits transient faults sensitivity evaluation. DAC Yannick Monnet, Marc Renaudin, Régis Leveugle
2005	A	`conf`	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain
2005	A	`conf`	FPGA Architecture for Multi-Style Asynchronous Logic. DATE N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin
2005	B	`conf`	GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin
2005	C	`conf`	Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2005	C	`conf`	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard
2005	C	`conf`	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC Jerome Quartana, Laurent Fesquet, Marc Renaudin
2005	—	`conf`	Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS David Rios-Arambula, Aurélien Buhrig, Marc Renaudin
2005	C	`conf`	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin
2005	—	`conf`	Wireless sensor network node with asynchronous architecture and vibration harvesting micro power generator. sOc-EUSAI Yasser Ammar, Aurélien Buhrig, Marcin Marzencki, Benoît Charlot, Skandar Basrour, Karine Matou, Marc Renaudin
2004	J	`jnl`	A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectron. J. Dhanistha Panyasak, Gilles Sicard, Marc Renaudin
2004	C	`conf`	Asynchronous Circuits Sensitivity to Fault Injection. IOLTS Yannick Monnet, Marc Renaudin, Régis Leveugle
2004	—	`conf`	Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin
2004	A	`conf`	High Security Smartcards. DATE Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain
2004	J	`jnl`	La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. Ann. des Télécommunications Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin
2004	—	`conf`	TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin
2003	—	`conf`	A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin
2003	—	`conf`	An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Siriani
2003	—	`conf`	Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
2003	—	`conf`	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS João Leonardo Fragoso, Gilles Sicard, Marc Renaudin
2003	—	`conf`	Statistic Implementation of QDI Asynchronous Primitives. PATMOS Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin
2003	—	`conf`	Validation of Asynchronous Circuit Specifications Using IF/CADP. VLSI-SoC (Selected Papers) Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
2003	C	`conf`	Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani
2002	—	`conf`	Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin
2002	A	`conf`	High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana
2002	B	`conf`	Implementing Asynchronous Circuits on LUT Based FPGAs. FPL Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland
2002	—	`conf`	Low-Power Asynchronous A/D Conversion. PATMOS Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard
2002	—	`conf`	Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin
2002	—	`conf`	Watershed parallel algorithm for asynchronous processors array. ICME (1) Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon
2001	J	`jnl`	A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE J. Solid State Circuits André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, Pascal Vivet
2001	A	`conf`	Low-power systems on chips (SOCs). DATE Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés
2001	C	`conf`	Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin
1999	—	`conf`	A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC Marc Renaudin, Pascal Vivet, Frédéric Robin
1998	—	`conf`	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC Marc Renaudin, Pascal Vivet, Frédéric Robin
1997	J	`jnl`	Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. Int. J. Pattern Recognit. Artif. Intell. Frédéric Robin, Gilles Privat, Marc Renaudin
1996	J	`jnl`	A new asynchronous pipeline scheme: application to the design of a self-timed ring divider. IEEE J. Solid State Circuits Marc Renaudin, Bachar El-Hassan, Alain Guyot
1996	—	`conf`	Asynchronous SRT Dividers: The Real Cost. ED&TC Hicham Boutamine, Alain Guyot, Bachar El-Hassan, Marc Renaudin
1996	Misc	`conf`	Self timed division and square-root extraction. VLSI Design Alain Guyot, Marc Renaudin, Bachar El-Hassan, Volker Levering
1995	C	`conf`	A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. ISCAS Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El-Hassan
1994	C	`conf`	The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. ISCAS Marc Renaudin, Bachar El-Hassan
1993	—	`conf`	A general time domain approach for the design of perfect reconstruction modulated filter banks. ICASSP (3) Michel Poize, Marc Renaudin, Patrick Venier
1993	—	`conf`	Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms. ASAP Patricia Planet, Gilles Privat, Marc Renaudin
1993	J	`jnl`	SMILE: A scalable microcontroller library element. Microprocess. Microprogramming A. K. Betts, Ivo Bolsens, Etienne Sicard, Marc Renaudin, Adrian Johnstone
1989	C	`conf`	Motion estimation VLSI architecture for image coding. ICCD Gilles Privat, Marc Renaudin