Marc Reichenbach

110 papers A 1B 2C 2Journal 33Unranked 66

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Integrating an open-source soft-GPU overlay with RISC-V control and high-bandwidth memory. J. Syst. Archit. Hector Gerardo Muñoz Hernandez, Mahdi Taheri, Muhammad Ali, Keyvan Shahin, Alireza Syavashi, Diana Göhringer, Marc Reichenbach, Christian Herglotz, Michael Hübner
2025	—	`conf`	Comparison of Bluetooth Low Energy (BLE), Wi-Fi, Serial and 5G in IoMT. BIOSTEC (2): HEALTHINF Nina Pearl Doe, Stefan Scharoba, Marc Reichenbach, Christian Herglotz
2025	—	`conf`	Design Space Exploration of a Direct Cached Memory Access Controller Optimized for HBM Memory Systems using TAPRE-HBM. CCMCC Gia Bao Thieu, Johannes Knödtel, Florian Rokohl, Marc Reichenbach, Guillermo Payá-Vayá
2025	J	`jnl`	Designing Intelligent Sensor Networks: A Comprehensive Survey of Sensing, Edge AI, and 5G+/6G Connectivity. IEEE Access Christian Herglotz, Ireneusz Jablonski, Reinhardt Karnapke, Keyvan Shahin, Marc Reichenbach
2025	J	`jnl`	Evaluation Pipeline for systematically searching for Anomaly Detection Systems. CoRR Florian Rokohl, Alexander Lehnert, Marc Reichenbach
2025	J	`jnl`	HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost. ACM Trans. Embed. Comput. Syst. Francesco Ratti, Johannes Knödtel, Marc Reichenbach
2025	—	`conf`	High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC. ASAP Liliia Almeeva, Alexander Lehnert, Ralf R. Müller, Marc Reichenbach
2025	—	`conf`	Multi-Dimensional Maturity Framework for Consumer ECG Devices. ICCE-Berlin Nina Pearl Doe, Kurt J. G. Schmailzl, Florian Rokohl, Marc Reichenbach, Christian Herglotz
2025	J	`jnl`	RISC-V CPU Design Using RRAM-CMOS Standard Cells. IEEE Trans. Very Large Scale Integr. Syst. Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Jianan Wen, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger
2025	—	`conf`	Towards Complete Open-Source Environments: FPGA-Based GPU Overlay Controlled by RISC-V. ARCS Hector Gerardo Muñoz Hernandez, Muhammad Ali, Keyvan Shahin, Alireza Siyavashi, Diana Göhringer, Marc Reichenbach, Christian Herglotz, Michael Hübner
2025	J	`jnl`	Towards a Memristor-Based Circuit Implementation of the Hindmarsh-Rose Model. Int. J. Circuit Theory Appl. Sebastian Jenderny, Daniel Reiser, Karlheinz Ochs, Marc Reichenbach
2024	—	`conf`	A Novel System Simulation Framework for HBM2 FPGA Platforms. SAMOS Hector Gerardo Muñoz Hernandez, Veronia Iskandar, Lukas Steiner, Philipp Holzinger, Matthias Jung, Diana Göhringer, Michael Hübner, Norbert Wehn, Marc Reichenbach
2024	—	`conf`	Area-Efficient Digital Design Using RRAM-CMOS Standard Cells. ISVLSI Markus Fritscher, Max Uhlmann, Philip Ostrovskyy, Daniel Reiser, Junchao Chen, Markus Andreas Schubert, Carsten Schulze, Gerhard Kahmen, Dietmar Fey, Marc Reichenbach, Milos Krstic, Christian Wenger
2024	—	`conf`	Cycle-Accurate FPGA Emulation of RRAM Crossbar Array: Efficient Device and Variability Modeling with Energy Consumption Assessment. LATS Jianan Wen, Fabian Luis Vargas, Fukun Zhu, Daniel Reiser, Andrea Baroni, Markus Fritscher, Eduardo Pérez, Marc Reichenbach, Christian Wenger, Milos Krstic
2024	—	`conf`	DeepTest: Using Machine Learning for Generating new Testsequences. MECO Jens Bielefeldt, Kai-Uwe Basener, Roman Krajewski, Hans-Werner Wiesbrock, Marc Reichenbach, Michael Hübner
2024	J	`jnl`	Design and analysis of an adaptive radiation resilient RRAM subsystem for processing systems in satellites. Des. Autom. Embed. Syst. Daniel Reiser, Junchao Chen, Johannes Knödtel, Andrea Baroni, Milos Krstic, Marc Reichenbach
2024	—	`conf`	HyRPF: Hybrid RRAM Prototyping on FPGA. SAMOS Daniel Reiser, Johannes Knödtel, Liliia Almeeva, Jianan Wen, Andrea Baroni, Milos Krstic, Marc Reichenbach
2024	J	`jnl`	Special Issue on SAMOS 2022. Int. J. Parallel Program. Alex Orailoglu, Marc Reichenbach, Matthias Jung
2024	A	`conf`	Towards an Embedded System for Failure Diagnosis in Drones Using AI and SAC-DM on FPGA. DATE Rafael Batista, Matthias Nickel, Alexander Lehnert, Sergio A. Pertuz, Marc Reichenbach, Diana Goehringer, Alisson Brito
2024	—	`conf`	Trusted Computing Architectures for IoT Devices. ARC An Braeken, Bruno da Silva, Laurent Segers, Johannes Knödtel, Marc Reichenbach, Cornelia Wulf, Sergio A. Pertuz, Diana Göhringer, Jo Vliegen, Md Masoom Rabbani, Nele Mentens
2024	J	`jnl`	XplAInable: Explainable AI Smoke Detection at the Edge. Big Data Cogn. Comput. Alexander Lehnert, Falko Gawantka, Jonas During, Franz Just, Marc Reichenbach
2023	—	`conf`	A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing. ARC Safdar Mahmood, Michael Hübner, Marc Reichenbach
2023	—	`conf`	A High-speed Low-power Sense Amplifier for the RRAM Array with Multi-level Reading Function using 130-nm Technology. ICECS Running Guo, Ruolan Jia, Stefan Pechmann, Marc Reichenbach, Amelie Hagelauer
2023	—	`conf`	A Modular Communication Architecture for Adaptive UAV Swarms. COINS Keyvan Shahin, Randolf Rotta, Oscar Archila, Pavlo Mykytyn, Matthias Nattke, Marc Reichenbach, Jörg Nolte, Roman Natarov
2023	J	`jnl`	An RRAM-based building block for reprogrammable non-uniform sampling ADCs. it Inf. Technol. Abhinav Vishwakarma, Markus Fritscher, Amelie Hagelauer, Marc Reichenbach
2023	—	`conf`	Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration. DroneSE/RAPIDO@HiPEAC Johannes Knödtel, Marc Reichenbach
2023	—	`ed.`	Embedded Computer Systems: Architectures, Modeling, and Simulation - 23rd International Conference, SAMOS 2023, Samos, Greece, July 2-6, 2023, Proceedings SAMOS Cristina Silvano, Christian Pilato, Marc Reichenbach
2023	J	`jnl`	Increasing the Robustness of TERO-TRNGs Against Process Variation. ACM Trans. Reconfigurable Technol. Syst. Christian Skubich, Peter Reichel, Marc Reichenbach
2023	—	`conf`	Linear Computation Coding for Convolutional Neural Networks. SSP Ralf R. Müller, Hans Rosenberger, Marc Reichenbach
2023	—	`conf`	More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding. ARC Alexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach
2023	J	`jnl`	Most Resource Efficient Matrix Vector Multiplication on FPGAs. IEEE Access Alexander Lehnert, Philipp Holzinger, Simon Pfenning, Ralf R. Müller, Marc Reichenbach
2023	—	`conf`	One-Transistor-Multiple-RRAM Cells for Energy-Efficient In-Memory Computing. NEWCAS Max Uhlmann, Emilio Pérez-Bosch Quesada, Markus Fritscher, Eduardo Pérez, Markus Andreas Schubert, Marc Reichenbach, Philip Ostrovskyy, Christian Wenger, Gerhard Kahmen
2023	—	`conf`	Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins. ISC Workshops Markus Fritscher, Alessandro Veronesi, Andrea Baroni, Jianan Wen, Thorsten Spätling, Mamathamba Kalishettyhalli Mahadevaiah, Norbert Herfurth, Eduardo Pérez, Markus Ulbricht, Marc Reichenbach, Amelie Hagelauer, Milos Krstic
2023	—	`conf`	TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. ARC Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Marc Reichenbach
2023	—	`conf`	Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations. NEWCAS Daniel Reiser, Marc Reichenbach, Tommaso Rizzi, Andrea Baroni, Markus Fritscher, Christian Wenger, Cristian Zambelli, Davide Bertozzi
2023	—	`conf`	Welcome Message from the Chairs. COINS Farshad Firouzi, Krishnendu Chakrabarty, Naghmeh Karimi, Bahareh J. Farahani, Diana Goehringer, Aurora Gil de Castro, Marc Reichenbach, Kun-Chih Chen
2022	—	`conf`	Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning. SAMOS Florian Fricke, Stefan Scharoba, Sebastian Rachuj, Andreas Konopik, Florian Kluge, Georg Hofstetter, Marc Reichenbach
2022	—	`conf`	Detecting Improvised Land-mines using Deep Neural Networks on GPR Image Dataset targeting FPGAs. NorCAS Safdar Mahmood, Stefan Scharoba, Jonas Schorlemer, Christian Schulz, Michael Hübner, Marc Reichenbach
2022	—	`conf`	EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis. SAMOS Lars Schwenger, Philipp Holzinger, Dietmar Fey, Hector Gerardo Muñoz Hernandez, Marc Reichenbach
2022	—	`conf`	Edge GPU based on an FPGA Overlay Architecture using PYNQ. SBCCI Hector Gerardo Muñoz Hernandez, Florian Fricke, Muhammed Al Kadi, Marc Reichenbach, Michael Hübner
2022	—	`ed.`	Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings SAMOS Alex Orailoglu, Matthias Jung, Marc Reichenbach
2022	—	`ed.`	Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings SAMOS Alex Orailoglu, Marc Reichenbach, Matthias Jung
2022	J	`jnl`	Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020). Int. J. Parallel Program. Marc Reichenbach, Matthias Jung, Alex Orailoglu
2022	J	`jnl`	InjectMeAI - Software Module of an Autonomous Injection Humanoid. Sensors Kwame Owusu Ampadu, Florian Rokohl, Safdar Mahmood, Marc Reichenbach, Michael Hübner
2022	J	`jnl`	Modeling and Fault Detection of Brushless Direct Current Motor by Deep Learning Sensor Data Fusion. Sensors Priscile Suawa, Tenia Meisel, Marcel Jongmanns, Michael Hübner, Marc Reichenbach
2022	C	`conf`	Suitability of ISAs for Data Paths Based on Redundant Number Systems: Is RISC-V the best? DSD Johannes Knödtel, Sebastian Rachuj, Marc Reichenbach
2021	B	`conf`	A Case for Function-as-a-Service with Disaggregated FPGAs. CLOUD Burkhard Ringlein, François Abel, Dionysios Diamantopoulos, Beat Weiss, Christoph Hagleitner, Marc Reichenbach, Dietmar Fey
2021	J	`jnl`	Adaptation Strategies for Personalized Gait Neuroprosthetics. Frontiers Neurorobotics Anne D. Koelewijn, Musa L. Audu, Antonio J. del Ama, Annalisa Colucci, Josep M. Font-Llagunes, Antonio Gogeascoechea, Sandra K. Hnat, Nathan S. Makowski, Juan C. Moreno, Mark J. Nandor, Roger D. Quinn, Marc Reichenbach, Ryan-David Reyes, Massimo Sartori, Surjo R. Soekadar, Ronald J. Triolo, Mareike Vermehren, Christian Wenger, Utku S. Yavuz, Dietmar Fey, Philipp Beckerle
2021	J	`jnl`	E = AI ERCIM News Marco Breiling, Bijoy Kundu, Marc Reichenbach
2021	—	`conf`	Fast HBM Access with FPGAs: Analysis, Architectures, and Applications. IPDPS Workshops Philipp Holzinger, Daniel Reiser, Tobias Hahn, Marc Reichenbach
2021	—	`conf`	Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks. SAMOS Markus Fritscher, Johannes Knödtel, Maen Mallah, Stefan Pechmann, Emilio Pérez-Bosch Quesada, Tommaso Rizzi, Christian Wenger, Marc Reichenbach
2021	J	`jnl`	RISC-V3: A RISC-V Compatible CPU With a Data Path Based on Redundant Number Systems. IEEE Access Marc Reichenbach, Johannes Knödtel, Sebastian Rachuj, Dietmar Fey
2021	—	`conf`	Simulating large neural networks embedding MLC RRAM as weight storage considering device variations. LASCAS Markus Fritscher, Johannes Knödtel, Daniel Reiser, Maen Mallah, Stefan Pechmann, Dietmar Fey, Marc Reichenbach
2021	C	`conf`	Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design. ISORC Steffen Vaas, Peter Ulbrich, Christian Eichler, Peter Wägemann, Marc Reichenbach, Dietmar Fey
2021	J	`jnl`	The HERA Methodology: Reconfigurable Logic in General-Purpose Computing. IEEE Access Philipp Holzinger, Marc Reichenbach
2021	J	`jnl`	Transparent FPGA Acceleration with TensorFlow. CoRR Simon Pfenning, Philipp Holzinger, Marc Reichenbach
2020	—	`conf`	A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories. MOCAST Johannes Knödtel, Markus Fritscher, Daniel Reiser, Dietmar Fey, Marco Breiling, Marc Reichenbach
2020	—	`ed.`	Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings SAMOS Alex Orailoglu, Matthias Jung, Marc Reichenbach
2020	—	`conf`	Impact of Performance Estimation on Fast Processor Simulators. SimuTools (2) Sebastian Rachuj, Dietmar Fey, Marc Reichenbach
2019	—	`conf`	A Generic Functional Simulation of Heterogeneous Systems. ARCS Sebastian Rachuj, Marc Reichenbach, Dietmar Fey
2019	—	`conf`	A Hardware Inference Accelerator for Temporal Convolutional Networks. NORCAS Rashid Ali, Maen Mallah, Martin Leyh, Philipp Holzinger, Marco Breiling, Marc Reichenbach, Dietmar Fey
2019	J	`jnl`	Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands. J. Signal Process. Syst. Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
2019	J	`jnl`	Heterogeneous Computing Utilizing FPGAs - A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms. J. Signal Process. Syst. Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
2019	—	`conf`	Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools. ICECS Markus Fritscher, Johannes Knödtel, Marc Reichenbach, Dietmar Fey
2018	—	`conf`	A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. ARCS Sebastian Rachuj, Christian Herglotz, Marc Reichenbach, André Kaup, Dietmar Fey
2018	—	`conf`	A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs. PATMOS Johannes Knödtel, Wolffhardt Schwabe, Tobias Lieske, Marc Reichenbach, Dietmar Fey
2018	J	`jnl`	A flexible mixed-signal image processing pipeline using 3D chip stacks. J. Real Time Image Process. Lan Shi, Christopher Soell, Benjamin Pfundt, Andreas Baenisch, Marc Reichenbach, Jürgen Seiler, Thomas Ussmueller, Robert Weigel
2018	—	`conf`	A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems. SAMOS Philipp Holzinger, Marc Reichenbach, Dietmar Fey
2018	—	`conf`	Autonomous Driving in the Curriculum of Computer Architecture. EWME Sebastian Rachuj, Marc Reichenbach, Steffen Vaas, Dietmar Fey
2018	J	`jnl`	Case study on memristor-based multilevel memories. Int. J. Circuit Theory Appl. Christopher Soell, Marc Reichenbach, Juergen Roeber, Amelie Hagelauer, Robert Weigel, Dietmar Fey
2018	—	`conf`	Comparison of Lane Detection Algorithms for ADAS Using Embedded Hardware Architectures. DASIP Marc Reichenbach, Lukas Liebischer, Steffen Vaas, Dietmar Fey
2018	J	`jnl`	IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures. J. Real Time Image Process. Christian Hartmann, Konrad Häublein, Marc Reichenbach, Dietmar Fey
2018	J	`jnl`	Modeling the Energy Consumption of the HEVC Decoding Process. IEEE Trans. Circuits Syst. Video Technol. Christian Herglotz, Dominic Springer, Marc Reichenbach, Benno Stabernack, André Kaup
2018	—	`conf`	Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems. Euro-Par Workshops Wolfgang Bauer, Philipp Holzinger, Marc Reichenbach, Steffen Vaas, Paul Hartke, Dietmar Fey
2017	J	`jnl`	Comprehensive curriculum for reconfigurable heterogeneous computer architecture education. IET Circuits Devices Syst. Benjamin Pfundt, Marc Reichenbach, Dietmar Fey
2017	J	`jnl`	Fast heterogeneous computing architectures for smart antennas. J. Syst. Archit. Marc Reichenbach, Maximilian Kasparek, Konrad Häublein, Jan Niklas Bauer, Mohammad Alawieh, Dietmar Fey
2017	—	`—`	Heterogene Rechnerarchitekturen für intelligente Kameras. Marc Reichenbach
2017	—	`conf`	LibHSA: One step towards mastering the era of heterogeneous hardware accelerators using FPGAs. DASIP Marc Reichenbach, Philipp Holzinger, Konrad Häublein, Tobias Lieske, Paul Blinzer, Dietmar Fey
2017	—	`conf`	Prototyping memristors in digital system with an FPGA-based testing environment. PATMOS Daniel Wust, Mehrdad Biglari, Johannes Knödtel, Marc Reichenbach, Christopher Söll, Dietmar Fey
2017	—	`conf`	System on chip generation for multi-sensor and sensor fusion applications. SAMOS Tobias Lieske, Benjamin Pfundt, Steffen Vaas, Marc Reichenbach, Dietmar Fey
2017	—	`conf`	The best of both: High-performance anc deterministic real-time executive by application-specific multi-core SoCs. DASIP Steffen Vaas, Peter Ulbrich, Marc Reichenbach, Dietmar Fey
2016	—	`conf`	An Application-Specific Instruction Set Processor for Power Quality Monitoring. IPDPS Workshops Steffen Vaas, Marc Reichenbach, Dietmar Fey
2016	—	`conf`	Dataflow optimization for programmable embedded image preprocessing accelerators. ReConFig Tobias Lieske, Marc Reichenbach, Burkhard Ringlein, Dietmar Fey
2016	—	`conf`	Dynamic pixel binning allows spatial and angular resolution tradeoffs to improve image quality in X-ray C-arm CT. ISBI Alexander Steg, Marc Reichenbach, Christopher Soell, Lan Shi, Andreas K. Maier, Christian Riess
2016	—	`conf`	Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. ARC Konrad Häublein, Christian Hartmann, Marc Reichenbach, Dietmar Fey
2016	—	`conf`	Hybrid code description for developing fast and resource efficient image processing architectures. SAMOS Konrad Häublein, Marc Reichenbach, Oliver Reiche, M. Akif Ozkan, Dietmar Fey, Frank Hannig, Jürgen Teich
2016	B	`conf`	Low-power analog smart camera sensor for edge detection. ICIP Christopher Soell, Lan Shi, Jürgen Röber, Marc Reichenbach, Robert Weigel, Amelie Hagelauer
2016	—	`conf`	Teaching heterogeneous computer architectures using smart camera systems. EWME Benjamin Pfundt, Marc Reichenbach, Christian Hartmann, Konrad Häublein, Dietmar Fey
2016	—	`conf`	The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs. ReConFig Steffen Vaas, Marc Reichenbach, Ulrich Margull, Dietmar Fey
2016	—	`conf`	Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits. MEMSYS Dietmar Fey, Marc Reichenbach, Christopher Söll, Mehrdad Biglari, Jürgen Röber, Robert Weigel
2015	J	`jnl`	A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures. CoRR Christian Hartmann, Anna Yupatova, Marc Reichenbach, Dietmar Fey, Reinhard German
2015	J	`jnl`	Automatic Optimization of Hardware Accelerators for Image Processing. CoRR Oliver Reiche, Konrad Häublein, Marc Reichenbach, Frank Hannig, Jürgen Teich, Dietmar Fey
2015	—	`conf`	Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing. IPDPS Workshops Christian Herglotz, Jürgen Seiler, André Kaup, Arne Hendricks, Marc Reichenbach, Dietmar Fey
2015	—	`conf`	FAUPU - A design framework for the development of programmable image processing architectures. ReConFig Marc Reichenbach, Tobias Lieske, Steffen Vaas, Konrad Häublein, Dietmar Fey
2015	—	`conf`	Framework for parameter analysis of FPGA-based image processing architectures. SAMOS Marc Reichenbach, Benjamin Pfundt, Dietmar Fey
2015	—	`conf`	Hardware-software co-simulation for medical x-ray control units. SimuTools Bruno Kleinert, Gholam Reza Rahimi, Marc Reichenbach, Dietmar Fey
2015	—	`conf`	Real-time correlation for locating systems utilizing heterogeneous computing architectures. DASIP Marc Reichenbach, Maximilian Kasparek, Mohammad Alawieh, Konrad Häublein, Dietmar Fey
2015	J	`jnl`	Synthesis and optimization of image processing accelerators using domain knowledge. J. Syst. Archit. Oliver Reiche, Konrad Häublein, Marc Reichenbach, Moritz Schmid, Frank Hannig, Jürgen Teich, Dietmar Fey
2014	—	`conf`	Designing and manufacturing of real embedded multi-core CPUs: A holistic teaching approach in computer architecture. EWME Marc Reichenbach, Benjamin Pfundt, Dietmar Fey
2014	—	`conf`	Fast and generic hardware architecture for stereo block matching applications on embedded systems. ReConFig Konrad Häublein, Marc Reichenbach, Dietmar Fey
2014	J	`jnl`	Fast image processing for optical metrology utilizing heterogeneous computer architectures. Comput. Electr. Eng. Marc Reichenbach, Ralf Seidler, Benjamin Pfundt, Dietmar Fey
2013	—	`conf`	Smart sensor architectures for embedded biosignal analysis. DASIP Benjamin Pfundt, Marc Reichenbach, Björn M. Eskofier, Dietmar Fey
2012	—	`conf`	A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. ISORC Workshops Michael Schmidt, Marc Reichenbach, Dietmar Fey
2012	—	`conf`	Heterogeneous computer architectures: An image processing pipeline for optical metrology. ReConFig Marc Reichenbach, Ralf Seidler, Dietmar Fey
2012	J	`jnl`	Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware. Concurr. Comput. Pract. Exp. Dietmar Fey, Marc Reichenbach, Marcus Komann, Ralf Seidler
2011	—	`conf`	Analytical Model for the Optimization of Self-Organizing Image Processing Systems Utilizing Cellular Automata. ISORC Workshops Marc Reichenbach, Michael Schmidt, Dietmar Fey
2011	—	`ch.`	Generic Emergent Computing in Chip Architectures. Organic Computing Marc Reichenbach, Ralf Seidler, Dietmar Fey, Benjamin Pfundt
2011	—	`conf`	Optimierung einer parallelen SIMD-Architektur für FPGA und ASIC. Informatiktage Benjamin Pfundt, Marc Reichenbach
2010	—	`conf`	Realizing Real-Time Centroid Detection of Multiple Objects with Marching Pixels Algorithms. ISORC Workshops Dietmar Fey, Marcus Komann, Marc Reichenbach, Ralf Seidler
2009	—	`conf`	Distributed vision with smart pixels. SCG Sándor P. Fekete, Dietmar Fey, Marcus Komann, Alexander Kröller, Marc Reichenbach, Christiane Schmidt