Marc Pons

14 papers A 3C 1Journal 2Unranked 8
YearRankTypeTitle / Venue / Authors
2022 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
ACM Trans. Embed. Comput. Syst.
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2021 J jnl
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs.
CoRR
Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini
2019 — conf
A 0.5 V 2.5 μW/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13nW/kB SRAM Retention in 55nm Deeply-Depleted Channel CMOS.
CICC
Marc Pons, Christoph Thomas Müller, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi
2019 A conf
Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW.
ISLPED
Jian Deng, Jean-Luc Nagel, Loïc Zahnd, Marc Pons, David Ruffieux, Claude Arm, Pascal Persechini, Stéphane Emery
2019 — conf
Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC.
PRIME
Christoph Thomas Müller, Marc Pons, David Ruffieux, Jean-Luc Nagel, Stéphane Emery, Andreas Burg, Shuuji Tanahashi, Yoshitaka Tanaka, Atsushi Takeuchi
2017 A conf
Ultra low power microelectronics for wearable and medical devices.
DATE
Pierre-François Rüedi, A. Bishof, Marcin K. Augustyniak, Pascal Persechini, Jean-Luc Nagel, Marc Pons, Stéphane Emery, Olivier Chételat
2016 — conf
Sub-threshold latch-based icyflex2 32-bit processor with wide supply range operation.
ESSCIRC
Marc Pons, Thanh-Chau Le, Claude Arm, Daniel Séverac, Jean-Luc Nagel, Marc-Nicolas Morgan, Stéphane Emery
2015 — conf
Sub-Threshold Design and Architectural Choices.
ISVLSI
Christian Piguet, Marc Pons, Daniel Séverac
2013 — conf
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation.
PATMOS
Marc Pons, Jean-Luc Nagel, Daniel Séverac, Marc-Nicolas Morgan, Daniel Sigg, Pierre-François Rüedi, Christian Piguet
2012 A conf
Fixed origin corner square inspection layout regularity metric.
DATE
Marc Pons, Marc-Nicolas Morgan, Christian Piguet
2012 — conf
Maximum delay variation temperature-aware standard cell design.
ICECS
Marc Pons, Jean-Luc Nagel, Christian Piguet
2011 — conf
Design of complex circuits using the Via-Configurable transistor array regular layout fabric.
SoCC
Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González
2010 C conf
VCTA: A Via-Configurable Transistor Array regular fabric.
VLSI-SoC
Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González
2007 — conf
Power supply noise and logic error probability.
ECCTD
Dennis Andrade, Ferran Martorell, Marc Pons, Francesc Moll, Antonio Rubio