Marc Boule

17 papers C 2Journal 6Unranked 9
YearRankTypeTitle / Venue / Authors
2016 — conf
Accelerating assertion assessment using GPUs.
HLDVT
Jason G. Tong, Marc Boule, Zeljko Zilic
2013 — conf
Efficient Data Encoding for Improving Fault Simulation Performance on GPUs.
ISED
Jason G. Tong, Marc Boule, Zeljko Zilic
2013 J jnl
Test compaction techniques for assertion-based test generation.
ACM Trans. Design Autom. Electr. Syst.
Jason G. Tong, Marc Boule, Zeljko Zilic
2010 J jnl
Defining and Providing Coverage for Assertion-Based Dynamic Verification.
J. Electron. Test.
Jason G. Tong, Marc Boule, Zeljko Zilic
2010 J jnl
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
2009 — conf
Airwolf-TG: A test generator for assertion-based dynamic verification.
HLDVT
Jason G. Tong, Marc Boule, Zeljko Zilic
2009 — conf
MYGEN: automata-based on-line test generator for assertion-based verification.
ACM Great Lakes Symposium on VLSI
Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic
2008 J jnl
Automata-based assertion-checker synthesis of PSL properties.
ACM Trans. Design Autom. Electr. Syst.
Marc Boule, Zeljko Zilic
2008 — conf
Proving and disproving assertion rewrite rules with automated theorem provers.
HLDVT
Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic
2007 — conf
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis.
ISQED
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
2007 J jnl
Debug enhancements in assertion-checker generation.
IET Comput. Digit. Tech.
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
2007 — conf
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation.
ASP-DAC
Marc Boule, Zeljko Zilic
2006 C conf
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.
ICCD
Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
2006 — conf
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties.
HLDVT
Marc Boule, Zeljko Zilic
2005 C conf
Incorporating Ef.cient Assertion Checkers into Hardware Emulation.
ICCD
Marc Boule, Zeljko Zilic
2002 J jnl
An FPGA Move Generator for the Game of Chess.
ICGA J.
Marc Boule, Zeljko Zilic
2002 — conf
An FPGA based move generator for the game of chess.
CICC
Marc Boule, Zeljko Zilic