Marc Belleville

28 papers A 1B 1C 2Journal 10Unranked 14

Year	Rank	Type	Title / Venue / Authors
2017	J	`jnl`	Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems. J. Low Power Electron. Marc Belleville, Anca Molnos, Gilles Sicard, Jean-Frédéric Christmann, Dominique Morche, Duy-Hieu Bui, Diego Puschini, Suzanne Lesecq, Edith Beigné
2016	J	`jnl`	Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era. ACM J. Emerg. Technol. Comput. Syst. Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville
2016	J	`jnl`	Ultra-wide voltage range pulse-triggered flip-flops and register file with tunable energy-delay target in 28 nm UTBB-FDSOI. Microelectron. J. Sebastien Bernard, Marc Belleville, Jean-Didier Legat, Alexandre Valentian, David Bol
2015	—	`conf`	Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit. PATMOS Soundous Chairat, Edith Beigné, Marc Belleville
2015	J	`jnl`	Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
2015	C	`conf`	Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits. RC Samer Houri, Gérard Billiot, Marc Belleville, Alexandre Valentian, Hervé Fanet
2014	J	`jnl`	A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations. J. Low Power Electron. Sebastien Bernard, Alexandre Valentian, David Bol, Jean-Didier Legat, Marc Belleville
2014	—	`conf`	Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature. PATMOS Sebastien Bernard, Marc Belleville, Alexandre Valentian, Jean-Didier Legat, David Bol
2013	—	`conf`	A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits. ICICDT Santhosh Onkaraiah, Marc Belleville, Marina Reyboz, Fabien Clermidy, Elisa Vianello, Jean-Michel Portal, Christophe Muller
2013	A	`conf`	A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits. DATE Smriti Joshi, Anne Lombardot, Marc Belleville, Edith Beigné, Stéphane Girard
2013	—	`conf`	A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	An efficient metric of setup time for pulsed flip-flops based on output transition time. ICICDT Sebastien Bernard, Alexandre Valentian, Marc Belleville, David Bol, Jean-Didier Legat
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2012	—	`conf`	A mixed LPDDR2 impedance calibration technique exploiting 28nm Fully-Depleted SOI Back-Biasing. ICICDT Dimitri Soussan, Alexandre Valentian, Sylvain Majcherczak, Marc Belleville
2012	—	`conf`	Design challenges for nano-scale devices. ESSDERC Marc Belleville, Olivier Thomas, Alexandre Valentian, Fabien Clermidy
2012	—	`conf`	Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring. ICECS Florent Dupont, Cyril Condemine, Jean-François Beche, Marc Belleville
2012	J	`jnl`	Selected Articles from the VARI 2011 Workshop. J. Low Power Electron. Nadine Azémard, Marc Belleville
2012	J	`jnl`	Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below. J. Low Power Electron. J. Mazurier, Olivier Weber, François Andrieu, Alain Toffoli, Olivier Thomas, Fabienne Allain, Jean-Philippe Noel, Marc Belleville, Olivier Faynot, T. Poiroux
2011	—	`conf`	Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard
2011	J	`jnl`	Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization. Microelectron. J. Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2010	—	`conf`	3D Integration for Digital and Imagers Circuits: Opportunities and Challenges. PATMOS Marc Belleville
2010	J	`jnl`	An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process. J. Low Power Electron. Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2010	J	`jnl`	Energy autonomous sensor systems: Towards a ubiquitous sensor technology. Microelectron. J. Marc Belleville, Hervé Fanet, Paolo Fiorini, Pierre Nicole, Marcel J. M. Pelgrom, Christian Piguet, Robert Hahn, Chris Van Hoof, Ruud J. M. Vullers, Marco Tartagni, Eugenio Cantatore
2009	—	`conf`	An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. PATMOS Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara
2009	—	`conf`	Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. PATMOS Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard
2009	—	`conf`	On-chip data compression for I.R. image sensors. ICECS Tristan Thabuis, Patrick Villard, Marc Belleville, Gilles Sicard, Frederic Pistone, Patrick Maillart, Gilbert Decaens
2008	—	`conf`	Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, Philippe Maurine, Nadine Azémard
2007	C	`conf`	Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology. ISCAS Olivier Thomas, Marina Reyboz, Marc Belleville