Manxin Li - RankMe

13 papers C 3Journal 2Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	An Easy-to-Drive Discrete-Time ADC Topology Using Digital Predictive Level-Shifting. ISCAS Manxin Li, Runpeng Gao, Calder Wilson, Amartya Basak, Evan C. Markwell, Matthew L. Johnston, Un-Ku Moon
2023	C	`conf`	A 16- Bit 100kHz Bandwidth Pseudo-Pseudo-Differential Delta-Sigma ADC. ISCAS Manxin Li, Calvin Yoji Lee, Hanyu Wang, Gabor C. Temes, Un-Ku Moon
2023	J	`jnl`	A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting. IEEE J. Solid State Circuits Manxin Li, Calvin Yoji Lee, Praveen Kumar Venkatachala, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon
2023	—	`conf`	A Rail-to-Rail 12MS 91.3dB SNDR 94.1dB DR Two-Step SAR ADC with Integrated Input Buffer Using Predictive Level-Shifting. ISSCC Manxin Li, Calvin Yoji Lee, Ahmed ElShater, Yuichi Miyahara, Kazuki Sobue, Koji Tomioka, Un-Ku Moon
2021	J	`jnl`	A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers. ASICON Yuting Yao, Jipeng Wei, Manxin Li, Shunli Ma, Fan Ye, Junyan Ren
2019	—	`conf`	SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors. ASICON Yuting Yao, Manxin Li, Tianxiang Wu, Hu Xu, Shunli Ma, Wenzhong Bao, Junyan Ren
2018	C	`conf`	A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren
2017	—	`conf`	A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC. ASICON Zhiyuan Dai, Hang Hu, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	A 12bit asynchronous SAR-incremental sub-range ADC. ASICON Manxin Li, Hang Hu, Zhiyuan Dai, Fan Ye, Junyan Ren
2017	—	`conf`	A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation. ASICON Hang Hu, Manxin Li, Zhiyuan Dai, Fan Ye, Junyan Ren
2017	—	`conf`	A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique. ASICON Hang Hu, Zhiyuan Dai, Manxin Li, Fan Ye, Junyan Ren
2017	—	`conf`	A stacked-packaged 16-channel ADC for ultrasound application. ASICON Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren