Manuel Valencia-Barrero

26 papers A 1C 4Journal 11Unranked 9

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations. Sensors Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
2021	J	`jnl`	Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA. IEEE Access Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, José Miguel Mora-Gutierrez, Manuel Valencia-Barrero, Carlos Jesús Jiménez-Fernández
2020	J	`jnl`	ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium. IEEE Trans. Circuits Syst. José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2020	J	`jnl`	An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero
2020	J	`jnl`	Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors Francisco Eugenio Potestad-Ordóñez, Manuel Valencia-Barrero, Carmen Baena Oliva, Pilar Parra Fernández, Carlos Jesús Jiménez-Fernández
2020	C	`conf`	Hamming-Code Based Fault Detection Design Methodology for Block Ciphers. ISCAS Francisco Eugenio Potestad-Ordóñez, Erica Tena-Sánchez, Ricardo Chaves, Manuel Valencia-Barrero, Antonio Acosta-Jiménez, Carlos Jesús Jiménez-Fernández
2018	—	`conf`	Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Carmen Baena Oliva, Pilar Parra Fernández, Manuel Valencia-Barrero
2017	J	`jnl`	Multiradix Trivium Implementations for Low-Power IoT Hardware. IEEE Trans. Very Large Scale Integr. Syst. José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2017	J	`jnl`	Trivium hardware implementations for power reduction. Int. J. Circuit Theory Appl. José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2017	J	`jnl`	Vulnerability Analysis of Trivium FPGA Implementations. IEEE Trans. Very Large Scale Integr. Syst. Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2016	C	`conf`	Fault attack on FPGA implementations of Trivium stream cipher. ISCAS Francisco Eugenio Potestad-Ordóñez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2012	—	`conf`	Low Power Implementation of Trivium Stream Cipher. PATMOS José Miguel Mora-Gutierrez, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2008	—	`ch.`	Logic Synthesis. Wiley Encyclopedia of Computer Science and Engineering Angel Barriga, Carlos Jesús Jiménez-Fernández, Manuel Valencia-Barrero
2007	—	`conf`	A switching noise vision of the optimization techniques for low-power synthesis. ECCTD Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2007	C	`conf`	Asymmetric clock driver for improved power and noise performances. ISCAS Javier Castro-Ramirez, Pilar Parra Fernández, Manuel Valencia-Barrero, Antonio J. Acosta
2005	J	`jnl`	Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
2002	—	`conf`	Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS Pilar Parra Fernández, Antonio J. Acosta, Manuel Valencia-Barrero
2001	—	`conf`	Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2001	A	`conf`	HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
2000	—	`conf`	Degradation Delay Model Extension to CMOS Gates. PATMOS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2000	—	`conf`	Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
1995	J	`jnl`	Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
1995	—	`conf`	New CMOS VLSI linear self-timed architectures. ASYNC Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
1993	C	`conf`	A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
1993	—	`conf`	Modeling of real bistables in VHDL. EURO-DAC Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas
1986	J	`jnl`	Asynchronous Modular Arbiter. IEEE Trans. Computers J. Calvo, José I. Acha, Manuel Valencia-Barrero