Manuel J. Bellido

30 papers A 1B 1C 3Journal 6Unranked 18

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	Address-encoded byte order. Microprocess. Microsystems David Guerrero Martos, German Cano-Quiveu, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido, Julian Viejo, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2016	J	`jnl`	Fast Hardware Implementations of Static P Systems. Comput. Informatics Juan Quiros, Sergey Verlan, Julian Viejo, Alejandro Millán, Manuel J. Bellido
2012	—	`conf`	Network Time Synchronization: A Full Hardware Approach. PATMOS Jorge Juan, Julian Viejo, Manuel J. Bellido
2011	J	`jnl`	Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. David Guerrero Martos, Alejandro Millán, Jorge Juan, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2010	J	`jnl`	Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. Alejandro Millán, Manuel J. Bellido, Jorge Juan, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2009	B	`conf`	Efficient techniques and methodologies for embedded system design usign free hardware and open standards. FPL Jose Ignacio Villar, Jorge Juan, Manuel J. Bellido
2008	—	`conf`	Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS Alejandro Millán, Jorge Juan, Manuel J. Bellido, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Julian Viejo
2007	—	`conf`	Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES Julian Viejo, Alejandro Millán, Manuel J. Bellido, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa, Alejandro Muñoz
2007	—	`conf`	Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa, Julian Viejo
2006	C	`conf`	Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES Julian Viejo, Manuel J. Bellido, Alejandro Millán, Enrique Ostúa, Jorge Juan, Paulino Ruiz-de-Clavijo, David Guerrero Martos
2004	—	`conf`	Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
2003	—	`conf`	Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán
2003	—	`conf`	Internode: Internal Node Logic Computational Model. Annual Simulation Symposium Alejandro Millán, Manuel J. Bellido, Jorge Juan-Chico, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
2002	—	`conf`	Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos
2002	—	`conf`	Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Alejandro Millán, David Guerrero Martos
2002	—	`ed.`	Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002 PATMOS Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
2002	—	`conf`	Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia
2001	—	`conf`	AUTODDM: automatic characterization tool for the delay degradation model. ICECS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
2001	—	`conf`	Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2001	A	`conf`	HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia-Barrero
2000	—	`conf`	Degradation Delay Model Extension to CMOS Gates. PATMOS Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero
2000	C	`conf`	Inertial and degradation delay model for CMOS logic gates. ISCAS Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia
2000	—	`conf`	Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits. PATMOS Antonio J. Acosta, Raúl Jiménez, Jorge Juan-Chico, Manuel J. Bellido, Manuel Valencia-Barrero
1998	—	`conf`	Efficient self-timed circuits based on weak NMOS-trees. ICECS Raúl Jiménez, Antonio J. Acosta, Angel Barriga, Manuel J. Bellido, Manuel Valencia
1996	—	`conf`	Multimedia System for Instruction and Learning Electronics. CALISCE P. Fortet, Manuel J. Bellido, Francisco Sivianes, A. V. Medina
1995	J	`jnl`	Modular Asynchronous Arbiter Insensitive to Metastability. IEEE Trans. Computers Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas, Antonio J. Acosta, Santiago Sánchez-Solano
1995	—	`conf`	New CMOS VLSI linear self-timed architectures. ASYNC Antonio J. Acosta, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas
1995	J	`jnl`	SODS: a new CMOS differential-type structure. IEEE J. Solid State Circuits Antonio J. Acosta, Manuel Valencia, Angel Barriga, Manuel J. Bellido, José L. Huertas
1993	C	`conf`	A New Faster Method for Calculating the Resolution Coefficient of CMOS Latches: Design of an Optimum Latch. ISCAS Manuel J. Bellido, Manuel Valencia-Barrero, Antonio J. Acosta, Angel Barriga, José Luis Huertas, Rafael Domínguez-Castro
1993	—	`conf`	Modeling of real bistables in VHDL. EURO-DAC Antonio J. Acosta, Angel Barriga, Manuel Valencia-Barrero, Manuel J. Bellido, José L. Huertas