Manuel J. Barragán

67 papers A 4B 8C 11Misc 4Journal 14Unranked 26

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Comprehensive Review of State-of-the-Art Harmonic Rejection Techniques in N-Path Mixers. LASCAS Malak Bouaamri, Fadel Mohsen, Imadeddine Bendjeddou, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel
2026	—	`conf`	RF Design-Oriented ACM Model Generation Using Parametric Test and Machine Learning Regression in 28nm FD-SOI CMOS Technology. LASCAS Catalin Andrei Dobrin, Deni Germano Alves Neto, D. Gaidioz, Philippe Cathelin, Sylvain Bourdel, Manuel J. Barragán
2025	—	`conf`	A Wideband Model for a Stacked Millimeter-Wave Transformer-based Power Combiner. PRIME Oumayma Belkhadra, Florent Cilici, Salvador Mir, Manuel J. Barragán, Gilles Montoriol, Emmanuel Pistono, Sylvain Bourdel
2025	—	`conf`	Automatic Generation of ACM Design-Oriented Models for MOS Transistors from Quasi-Static Wafer-Level Characterization Data. PRIME Catalin Andrei Dobrin, D. Gaidioz, Philippe Cathelin, Florence Podevin, Sylvain Bourdel, Manuel J. Barragán
2025	—	`conf`	Multi-Agent Reinforcement Learning for Performance Calibration and Optimization of Integrated mmW Power Amplifiers. ATS Valentin Coppola, Florent Cilici, Sylvain Bourdel, Estelle Lauga-Larroze, Salvador Mir, Florence Podevin, Manuel J. Barragán
2024	—	`conf`	An Integrated Miniaturized VNA for On-Chip PA Mismatch Measurement. NewCAS Oumayma Belkhadra, Gilles Montoriol, Emmanuel Pistone, Hugo Vallee, Florent Cilici, Manuel J. Barragán, Salvador Mir, Sylvain Bourdel
2024	—	`conf`	Design and Evaluation of a 10 GHz LNA with Balun and Diodes for HBM and CDM ESD Protection in 28 nm CMOS FD-SOI. SBCCI Thalis Da C. Guedes, Johan Bourgeat, Manuel J. Barragán, Jean-Marc Duchamp, Philippe Ferrari
2024	J	`jnl`	Design-Oriented Single-Piece 5-DC-Parameter MOSFET Model. IEEE Access Deni Germano Alves Neto, Mohamed Khalil Bouchoucha, Gabriel Maranhão, Manuel J. Barragán, Márcio Cherem Schneider, Andreia Cathelin, Sylvain Bourdel, Carlos Galup-Montoro
2024	C	`conf`	Dynamic Analysis of RF CMOS Inverter-Based Ring Oscillators using an All-Region MOSFET Charge-Based Model in 28nm FD-SOI CMOS. ISCAS Julien Poupon, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel
2023	—	`conf`	A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE. NEWCAS Deni Germano Alves Neto, Cristina Missel Adotnes, Gabriel Maranhão, Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Márcio Cherem Schneider, Sylvain Bourdel, Carlos Galup-Montoro
2023	C	`conf`	A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell. ISCAS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2023	—	`conf`	A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA. NEWCAS Ankush Mamgain, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Jai Narayan Tripathi
2023	—	`conf`	A wideband sub-6GHz continuously tunable gm-boosted CG Low Noise Amplifier in 28 nm FD-SOI CMOS technology. ESSCIRC Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel
2023	J	`jnl`	Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge". IEEE Access Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
2023	—	`conf`	Design-oriented model for short-channel MOS transistors based on inversion charge. LASCAS Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
2023	C	`conf`	Performance benchmark of State-of-the-art Sub-6-GHz wideband LNAs Based on an Extensive Survey. ISCAS Mohamed Khalil Bouchoucha, Mathieu Coustans, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel
2023	C	`conf`	Resistive Feedback LNA design using a 7-parameter design-oriented model for advanced technologies. ISCAS Mohamed Khalil Bouchoucha, Dayana A. Pino-Monroy, Patrick Scheer, Philippe Cathelin, Jean-Michel Fournier, Manuel J. Barragán, Andreia Cathelin, Sylvain Bourdel
2023	—	`conf`	Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation. LATS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2023	—	`conf`	Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. LATS Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán
2022	—	`conf`	A methodology for defect detection in analog circuits based on causal feature selection. ICECS 2022 Gildas Léger, Antonio J. Ginés, Valentin Gutierrez, Manuel J. Barragán
2022	C	`conf`	A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. VLSI-SoC Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán
2022	J	`jnl`	Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge. IEEE Access Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel
2022	Misc	`conf`	Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
2022	—	`conf`	N-Path Mixer with Wide Rejection Including the 7 NEWCAS Ali Al Shakoush, Sana Ibrahim, Serge Subias, Florence Podevin, Manuel J. Barragán, Dayana A. Pino-Monroy, Imadeddine Bendjeddou, Estelle Lauga-Larroze, Laurent Fesquet, Thierry Taris, Sylvain Bourdel
2022	—	`conf`	On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators. ATS Ankush Mamgain, Salvador Mir, Jai Narayan Tripathi, Manuel J. Barragán
2022	B	`conf`	Special Session on RF/5G Test. ETS William R. Eisenstadt, Mark Roos, Devin Morris, José Luis González-Jiménez, Christopery Mounet, Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Salvador Mir, Sylvain Bourdel, Marc Margalef-Rovira, Issa Alaji, Haitham Ghanem, Guillaume Ducournau, Christophe Gaquière
2021	—	`conf`	A gm/ID Design Methodology for 28 nm FD-SOI CMOS Resistive Feedback LNAs. ICECS Sylvain Bourdel, Serge Subias, Mohamed Khalil Bouchoucha, Manuel J. Barragán, Andreia Cathelin, Carlos Galup-Montoro
2021	B	`conf`	Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation. ETS Ankush Mamgain, Manuel J. Barragán, Salvador Mir
2021	J	`jnl`	Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2020. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Pierre David, Manuel J. Barragán
2021	—	`conf`	Integrated Wideband Millimeter-Wave Bias-Tee - Application to Distributed Amplifier Biasing. NEWCAS Mohamad El-Chaar, Antonio Augusto Lisboa de Souza, Manuel J. Barragán, Florence Podevin, Sylvain Bourdel, Jean-Daniel Arnould
2021	—	`conf`	mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs. NEWCAS Marc Margalef-Rovira, Christophe Gaquière, Antonio Augusto Lisboa de Souza, Loic Vincent, Manuel J. Barragán, Emmanuel Pistono, Florence Podevin, Philippe Ferrari
2021	J	`jnl`	mm-Wave Through-Load Element for On-Wafer Measurement Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Marc Margalef-Rovira, Olivier Occello, Abdelhalim A. Saadi, Vanessa Avramovic, Sylvie Lépilliet, Loic Vincent, Manuel J. Barragán, Emmanuel Pistono, Sylvain Bourdel, Christophe Gaquière, Philippe Ferrari
2020	C	`conf`	A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
2020	J	`jnl`	Design of a 77-GHz LC-VCO With a Slow-Wave Coplanar Stripline-Based Inductor. IEEE Trans. Circuits Syst. I Regul. Pap. Ekta Sharma, Abdelhalim A. Saadi, Marc Margalef-Rovira, Emmanuel Pistono, Manuel J. Barragán, Antonio Augusto Lisboa de Souza, Philippe Ferrari, Sylvain Bourdel
2020	B	`conf`	On-chip reduced-code static linearity test of V ETS Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir
2020	—	`conf`	Static linearity BIST for V NEWCAS Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir
2020	—	`conf`	mm-Wave Through-Load Switch for in-situ Vector Network Analyzer on a 55-nm BiCMOS Technology. NEWCAS Marc Margalef-Rovira, Abdelhalim A. Saadi, Sylvain Bourdel, Manuel J. Barragán, Emmanuel Pistono, Christophe Gaquière, Philippe Ferrari
2019	B	`conf`	A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology. ETS Hani Malloug, Manuel J. Barragán, Salvador Mir
2019	—	`conf`	Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits. SMACD Florent Cilici, Gildas Léger, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
2019	—	`conf`	Feature selection and feature design for machine learning indirect test: a tutorial review. SMACD Manuel J. Barragán, Gildas Léger
2019	J	`jnl`	Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. IEEE Trans. Very Large Scale Integr. Syst. Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir
2019	A	`conf`	On the use of causal feature selection in the context of machine-learning indirect test. DATE Manuel J. Barragán, Gildas Léger, Florent Cilici, Estelle Lauga-Larroze, Sylvain Bourdel, Salvador Mir
2019	C	`conf`	Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs. VLSI-SoC Renato S. Feitoza, Manuel J. Barragán, Salvador Mir
2019	C	`conf`	Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration. ISCAS Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel, Gildas Léger
2018	Misc	`conf`	An oscillation-based test technique for on-chip testing of mm-wave phase shifters. VTS Marc Margalef-Rovira, Manuel J. Barragán, Ekta Sharma, Philippe Ferrari, Emmanuel Pistono, Sylvain Bourdel
2018	B	`conf`	Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits. ETS Florent Cilici, Manuel J. Barragán, Salvador Mir, Estelle Lauga-Larroze, Sylvain Bourdel
2018	J	`jnl`	Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing. J. Electron. Test. Ke Huang, Manuel J. Barragán
2018	C	`conf`	Mixed-signal test automation: Are we there yet? ISCAS Gildas Léger, Manuel J. Barragán
2018	J	`jnl`	Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. J. Electron. Test. Hani Malloug, Manuel J. Barragán, Salvador Mir
2018	C	`conf`	Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter. IOLTS Renato S. Feitoza, Manuel J. Barragán, Salvador Mir, Daniel Dzahini
2017	Misc	`conf`	Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs. VTS Guillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragán, Salvador Mir
2017	J	`jnl`	Guest Editorial: Analog, Mixed-Signal and RF Testing. J. Electron. Test. Manuel J. Barragán, William R. Eisenstadt
2017	B	`conf`	Mixed-signal BIST computation offloading using IEEE 1687. ETS Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir
2017	A	`conf`	On the limits of machine learning-based test: A calibrated mixed-signal system case study. DATE Manuel J. Barragán, Gildas Léger, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda
2016	J	`jnl`	A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. J. Electron. Test. Guillaume Renaud, Manuel J. Barragán, Asma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Hervé Naudet
2016	J	`jnl`	A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Manuel J. Barragán, Rshdee Alhakim, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2016	J	`jnl`	Brownian distance correlation-directed search: A fast feature selection technique for alternate test. Integr. Gildas Léger, Manuel J. Barragán
2016	B	`conf`	Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator. ETS Antonio J. Ginés, Eduardo J. Peralías, Gildas Léger, Adoración Rueda, Guillaume Renaud, Manuel J. Barragán, Salvador Mir
2016	J	`jnl`	Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. IEEE Des. Test Manuel J. Barragán, Haralampos-G. D. Stratigopoulos, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2016	B	`conf`	Questioning the reliability of Monte Carlo simulation for machine learning test validation. ETS Gildas Léger, Manuel J. Barragán
2015	A	`conf`	Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. ITC Haralampos-G. D. Stratigopoulos, Manuel J. Barragán, Salvador Mir, Hervé Le Gall, Neha Bhargava, Ankur Bal
2015	A	`conf`	Feature selection for alternate test using wrappers: application to an RF LNA case study. DATE Manuel J. Barragán, Gildas Léger
2015	Misc	`conf`	Special session: Hot topics: Statistical test methods. VTS Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
2014	C	`conf`	Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs. VLSI-SoC Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2014	—	`conf`	On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test. ATS Guillaume Renaud, Manuel J. Barragán, Salvador Mir, Marc Sabut
2014	—	`conf`	Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST. VLSI-SoC (Selected Papers) Matthieu Dubois, Haralampos-G. D. Stratigopoulos, Salvador Mir, Manuel J. Barragán
2013	—	`conf`	Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique. LASCAS Manuel J. Barragán, Gildas Léger, Diego Vázquez, Adoración Rueda