Manuel Eggimann

30 papers A 2C 2Journal 19Unranked 6
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
CoRR
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET.
IEEE J. Solid State Circuits
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET.
CoRR
Paul Scheffler, Thomas Benz, Viviane Potocnik, Tim Fischer, Luca Colagrande, Nils Wistoff, Yichao Zhang, Luca Bertaccini, Gianmarco Ottavi, Manuel Eggimann, Matheus A. Cavalcante, Gianna Paulin, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
IEEE J. Solid State Circuits
Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2024 — conf
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
VLSI Technology and Circuits
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 J jnl
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.
CoRR
Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2024 A conf
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
DATE
Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini
2024 J jnl
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine.
IEEE J. Solid State Circuits
Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023 — conf
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.
ISSCC
Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
2023 J jnl
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.
CoRR
Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
2023 — —
Near-Memory Computing Architectures and Circuits for Ultra-Low Power Near-Sensor Processors.
Manuel Eggimann
2023 J jnl
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
CoRR
Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini
2023 J jnl
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine.
CoRR
Arpan Suravi Prasad, Moritz Scherer, Francesco Conti, Davide Rossi, Alfio Di Mauro, Manuel Eggimann, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2023 — conf
Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS.
ESSCIRC
Moritz Scherer, Manuel Eggimann, Alfio Di Mauro, Arpan Suravi Prasad, Francesco Conti, Davide Rossi, Jorge Tomás Gómez, Ziyun Li, Syed Shakib Sarwar, Zhao Wang, Barbara De Salvo, Luca Benini
2022 J jnl
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021 — conf
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
ISSCC
Davide Rossi, Francesco Conti, Manuel Eggimann, Stefan Mach, Alfio Di Mauro, Marco Guermandi, Giuseppe Tagliavini, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2021 J jnl
A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Manuel Eggimann, Abbas Rahimi, Luca Benini
2021 J jnl
A 5 μW Standard Cell Memory-based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing.
CoRR
Manuel Eggimann, Abbas Rahimi, Luca Benini
2021 J jnl
ImpediSense: A long lasting wireless wearable bio-impedance sensor node.
Sustain. Comput. Informatics Syst.
Kanika S. Dheman, Philipp Mayer, Manuel Eggimann, Simone Schuerle, Michele Magno
2021 J jnl
TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition With Short Range Radars.
IEEE Internet Things J.
Moritz Scherer, Michele Magno, Jonas Erb, Philipp Mayer, Manuel Eggimann, Luca Benini
2021 J jnl
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR
Davide Rossi, Francesco Conti, Manuel Eggimann, Alfio Di Mauro, Giuseppe Tagliavini, Stefan Mach, Marco Guermandi, Antonio Pullini, Igor Loi, Jie Chen, Eric Flamand, Luca Benini
2020 A conf
InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy Harvesting.
DATE
Michele Magno, Xiaying Wang, Manuel Eggimann, Lukas Cavigelli, Luca Benini
2020 J jnl
TinyRadarNN: Combining Spatial and Temporal Convolutional Neural Networks for Embedded Gesture Recognition with Short Range Radars.
CoRR
Moritz Scherer, Michele Magno, Jonas Erb, Philipp Mayer, Manuel Eggimann, Luca Benini
2019 — conf
A RISC-V Based Open Hardware Platform for Always-On Wearable Smart Sensing.
IWASI
Manuel Eggimann, Stefan Mach, Michele Magno, Luca Benini
2019 C conf
An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications.
ISCAS
Mario Osta, Ali Ibrahim, Michele Magno, Manuel Eggimann, Antonio Pullini, Paolo Gastaldo, Maurizio Valle
2019 J jnl
HR-SAR-Net: A Deep Neural Network for Urban Scene Segmentation from High-Resolution SAR Data.
CoRR
Xiaying Wang, Lukas Cavigelli, Manuel Eggimann, Michele Magno, Luca Benini
2019 — conf
Low Power Embedded Gesture Recognition Using Novel Short-Range Radar Sensors.
IEEE SENSORS
Manuel Eggimann, Jonas Erb, Philipp Mayer, Michele Magno, Luca Benini
2018 C conf
Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS.
ISCAS
Manuel Eggimann, Christelle Gloor, Florian Scheidegger, Lukas Cavigelli, Michael Schaffner, Aljosa Smolic, Luca Benini
2017 J jnl
Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS.
CoRR
Manuel Eggimann, Christelle Gloor, Florian Scheidegger, Lukas Cavigelli, Michael Schaffner, Aljosa Smolic, Luca Benini