Manuel E. Acacio

127 papers A* 7A 11B 6C 13Misc 11Journal 49Unranked 28

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs. HPCA Nicolás Meseguer, Daoxuan Xu, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio
2025	—	`conf`	ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs. GPGPU@PPoPP Nicolás Meseguer, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio
2025	A*	`conf`	No Rush in Executing Atomic Instructions. HPCA Ashkan Asgharzadeh, Josué Feliu, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros
2025	J	`jnl`	Precise characterization of coherence activity in multicores using gem5. J. Supercomput. Joaquín Ferrer, Juan M. Cebrian, Ricardo Fernández-Pascual, Manuel E. Acacio
2025	C	`conf`	QuFi: Adaptive Tiled Gustavson Output Reuse for Edge Sparse DNN Accelerators. ICCD Adrián Navarro, José Cano, José L. Abellán, Manuel E. Acacio
2025	J	`jnl`	WoperTM: Got Nacks? Use Them! IEEE Comput. Archit. Lett. Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	A*	`conf`	Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	J	`jnl`	On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2023	B	`conf`	CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
2023	J	`jnl`	Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. CoRR Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna
2023	—	`conf`	Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing. ASPLOS (3) Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2023	J	`jnl`	STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2023	J	`jnl`	Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
2022	J	`jnl`	Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
2022	C	`conf`	Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	J	`jnl`	DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	A	`conf`	Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators. IPDPS Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna
2021	J	`jnl`	A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators. CoRR Raveesh Garg, Eric Qin, Francisco Muñoz-Martínez, Robert Guirado, Akshay Jain, Sergi Abadal, José L. Abellán, Manuel E. Acacio, Eduard Alarcón, Sivasankaran Rajamanickam, Tushar Krishna
2021	—	`conf`	A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators. NOCS Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2021	A*	`conf`	ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
2021	—	`conf`	STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IISWC Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2021	J	`jnl`	STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators. IEEE Comput. Archit. Lett. Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2020	J	`jnl`	Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2020	J	`jnl`	PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2020	J	`jnl`	STONNE: A Detailed Architectural Simulator for Flexible Neural Network Accelerators. CoRR Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2019	—	`conf`	CNN-SIM: A Detailed Arquitectural Simulator of CNN Accelerators. Euro-Par Workshops Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio
2019	J	`jnl`	Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems. Concurr. Comput. Pract. Exp. Manuel E. Acacio, Julio Sahuquillo
2019	J	`jnl`	InsideNet: A tool for characterizing convolutional neural networks. Future Gener. Comput. Syst. Francisco Muñoz-Martínez, José L. Abellán, Manuel E. Acacio
2019	J	`jnl`	Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio
2018	J	`jnl`	On the Parallelization of Stream Compaction on a Low-Cost SDC Cluster. Sci. Program. Gregorio Bernabé, Manuel E. Acacio
2018	J	`jnl`	Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster. J. Supercomput. Gregorio Bernabé, Raúl Hernández, Manuel E. Acacio
2018	J	`jnl`	Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio
2018	C	`conf`	SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors. PDP Francisco Muñoz-Martínez, Manuel E. Acacio
2017	J	`jnl`	A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. Juan M. Cebrian, Ricardo Fernández-Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros
2017	J	`jnl`	To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2017	A	`conf`	Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	J	`jnl`	Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	—	`conf`	Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2015	J	`jnl`	Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
2015	J	`jnl`	DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. Alberto Ros, Manuel E. Acacio
2015	B	`conf`	Early Experiences with Separate Caches for Private and Shared Data. e-Science Juan M. Cebrian, Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio
2015	—	`ch.`	Efficient Hardware-Supported Synchronization Mechanisms for Manycores. Handbook on Data Centers José L. Abellán, Juan Fernández, Manuel E. Acacio
2015	J	`jnl`	Fast and efficient commits for Lazy-Lazy hardware transactional memory. J. Supercomput. Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio
2015	—	`ch.`	Hardware Approaches to Transactional Memory in Chip Multiprocessors. Handbook on Data Centers J. Rubén Titos Gil, Manuel E. Acacio
2014	—	`conf`	Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2014	J	`jnl`	Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. J. Supercomput. Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2014	J	`jnl`	ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	—	`conf`	Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. ARCS Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández
2013	J	`jnl`	Design of an efficient communication infrastructure for highly contended locks in many-core CMPs. J. Parallel Distributed Comput. José L. Abellán, Juan Fernández, Manuel E. Acacio
2013	—	`conf`	ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio
2013	J	`jnl`	Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2013	Misc	`conf`	Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio
2013	J	`jnl`	Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2013	J	`jnl`	On the design of energy-efficient hardware transactional memory systems. Concurr. Comput. Pract. Exp. Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2013	—	`conf`	Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par Mario Lodde, José Flich, Manuel E. Acacio
2012	A	`conf`	ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
2012	—	`conf`	An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. IPDPS Workshops Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández Maimó, Ricardo Fernández-Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena
2012	A	`conf`	Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. DATE José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini
2012	—	`conf`	Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par Mario Lodde, José Flich, Manuel E. Acacio
2012	C	`conf`	Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández
2012	J	`jnl`	Efficient Hardware Barrier Synchronization in Many-Core CMPs. IEEE Trans. Parallel Distributed Syst. José L. Abellán, Juan Fernández, Manuel E. Acacio
2012	J	`jnl`	Extending Magny-Cours Cache Coherence. IEEE Trans. Computers Alberto Ros, Blas Cuesta Saez, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
2012	J	`jnl`	Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012	—	`conf`	Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. NOCS Mario Lodde, José Flich, Manuel E. Acacio
2012	J	`jnl`	Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. J. Supercomput. José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon
2012	C	`conf`	Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio
2012	A*	`conf`	π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	B	`conf`	Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	A	`conf`	GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs. IPDPS José L. Abellán, Juan Fernández, Manuel E. Acacio
2011	B	`conf`	Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2011	—	`conf`	The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström
2011	A	`conf`	ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström
2010	J	`jnl`	A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. Alberto Ros, Manuel E. Acacio, José M. García
2010	B	`conf`	A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs. ICPP José L. Abellán, Juan Fernández, Manuel E. Acacio
2010	J	`jnl`	A scalable organization for distributed directories. J. Syst. Archit. Alberto Ros, Manuel E. Acacio, José M. García
2010	C	`conf`	Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio
2010	J	`jnl`	Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. J. Supercomput. José L. Abellán, Juan Fernández, Manuel E. Acacio
2010	J	`jnl`	Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distributed Syst. Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato
2010	Misc	`conf`	EMC HiPC Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
2010	—	`conf`	Efficient and scalable barrier synchronization for many-core CMPs. Conf. Computing Frontiers José L. Abellán, Juan Fernández, Manuel E. Acacio
2010	C	`conf`	Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. PDP Antonio Flores, Juan L. Aragón, Manuel E. Acacio
2010	—	`conf`	Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops Alberto Ros, Manuel E. Acacio
2010	J	`jnl`	Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. J. Syst. Archit. Antonio Flores, Manuel E. Acacio, Juan L. Aragón
2010	J	`jnl`	Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. IEEE Trans. Computers Antonio Flores, Juan L. Aragón, Manuel E. Acacio
2009	C	`conf`	A Parallel Implementation of the 2D Wavelet Transform Using CUDA. PDP Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio
2009	—	`conf`	Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT Alberto Ros, Manuel E. Acacio, José M. García
2009	Misc	`conf`	Distance-aware round-robin mapping for large NUCA caches. HiPC Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García
2009	—	`conf`	Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. Euro-Par Epifanio Gaona-Ramírez, Juan Fernández, Manuel E. Acacio
2009	A	`conf`	Speculation-based conflict resolution in hardware transactional memory. IPDPS J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
2008	A	`conf`	A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato
2008	B	`conf`	Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP Antonio Flores, Manuel E. Acacio, Juan L. Aragón
2008	J	`jnl`	An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J. Supercomput. Antonio Flores, Juan L. Aragón, Manuel E. Acacio
2008	C	`conf`	CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. PDP José L. Abellán, Juan Fernández, Manuel E. Acacio
2008	C	`conf`	Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco
2008	—	`conf`	Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. ICCS (1) José L. Abellán, Juan Fernández, Manuel E. Acacio
2008	A	`conf`	DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS Alberto Ros, Manuel E. Acacio, José M. García
2008	Misc	`conf`	Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC J. Rubén Titos Gil, Manuel E. Acacio, José M. García
2008	J	`jnl`	Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distributed Syst. Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato
2008	Misc	`conf`	Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato
2008	—	`conf`	Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. CSC Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco
2008	—	`conf`	Scalable Directory Organization for Tiled CMP Architectures. CDES Alberto Ros, Manuel E. Acacio, José M. García
2008	J	`jnl`	Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García
2007	A*	`conf`	A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José Duato
2007	J	`jnl`	An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Comput. Gregorio Bernabé, Ricardo Fernández-Pascual, José M. García, Manuel E. Acacio, José González
2007	Misc	`conf`	Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC Alberto Ros, Manuel E. Acacio, José M. García
2007	Misc	`conf`	Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC Antonio Flores, Juan L. Aragón, Manuel E. Acacio
2007	—	`conf`	Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) Antonio Flores, Juan L. Aragón, Manuel E. Acacio
2006	—	`conf`	An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers Alberto Ros, Manuel E. Acacio, José M. García
2006	—	`conf`	On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS Francisco J. Villa, Manuel E. Acacio, José M. García
2005	—	`conf`	A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par Alberto Ros, Manuel E. Acacio, José M. García
2005	J	`jnl`	A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distributed Syst. Manuel E. Acacio, José González, José M. García, José Duato
2005	J	`jnl`	Evaluating IA-32 web servers through simics: a practical experience. J. Syst. Archit. Francisco J. Villa, Manuel E. Acacio, José M. García
2005	C	`conf`	Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. HPCC Francisco J. Villa, Manuel E. Acacio, José M. García
2005	C	`conf`	Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP Ricardo Fernández-Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio
2004	J	`jnl`	An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distributed Syst. Manuel E. Acacio, José González, José M. García, José Duato
2004	Misc	`conf`	On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. International Conference on Computational Science Francisco J. Villa, Manuel E. Acacio, José M. García
2002	A	`conf`	A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS Manuel E. Acacio, José González, José M. García, José Duato
2002	J	`jnl`	MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. Future Gener. Comput. Syst. Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel
2002	A	`conf`	Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC Manuel E. Acacio, José González, José M. García, José Duato
2002	C	`conf`	Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP Manuel E. Acacio, José González, José M. García, José Duato
2002	—	`conf`	The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT Manuel E. Acacio, José González, José M. García, José Duato
2001	A*	`conf`	A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA Manuel E. Acacio, José González, José M. García, José Duato
1999	Misc	`conf`	A Performance Evaluation of P-EDR in Different Parallel Environments. PDPTA Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel
1999	—	`conf`	An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. ACPC Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel
1999	—	`conf`	P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. IPPS/SPDP Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte
1999	Misc	`conf`	The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. PDPTA Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte
1999	Misc	`conf`	The Parallel EM Algorithm and its Applications in Computer Vision. PDPTA Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio