Mansi Jhamb

14 papers Journal 14
YearRankTypeTitle / Venue / Authors
2026 J jnl
Low power post quantum cryptography on reconfigurable devices for cyber physical system in IoT.
Integr.
Ankita Sarkar, Mansi Jhamb
2025 J jnl
A novel ultra-low power post quantum approach using artificial intelligence based key generation for cyber physical system in Internet of things.
Sustain. Comput. Informatics Syst.
Ankita Sarkar, Mansi Jhamb
2025 J jnl
Design of extremely low power, high compliance and low noise current mirror.
Comput. Electr. Eng.
Pritty, Mansi Jhamb
2025 J jnl
Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application.
Integr.
B. Jyothi, B. V. Ramana Reddy, Mansi Jhamb
2024 J jnl
A Novel and Voltage Resilient Design of Ultra-High-Speed Low Power Keeper Based Full Adder.
Circuits Syst. Signal Process.
Uma Sharma, Mansi Jhamb
2024 J jnl
Improved RSA with Enhanced Security on STM32 @ 84MHz.
J. Circuits Syst. Comput.
Ankita Sarkar, Mansi Jhamb
2023 J jnl
A 0.8-Volt 29.52-μW Current Mirror-Based OTA Design for Biomedical Applications.
J. Circuits Syst. Comput.
Mansi Jhamb
2023 J jnl
Efficient Design of FGMOS-Based Low-Power Low-Voltage XOR Gate.
Circuits Syst. Signal Process.
Uma Sharma, Mansi Jhamb
2022 J jnl
A Novel Design of Voltage and Temperature Resilient 9-T Domino Logic XOR /XNOR Cell.
Circuits Syst. Signal Process.
Uma Sharma, Mansi Jhamb
2022 J jnl
Ultra low power design of multi-valued logic circuit for binary interfaces.
J. King Saud Univ. Comput. Inf. Sci.
Mansi Jhamb, Ratnesh Mohan
2021 J jnl
Ultra low power current mirror design with enhanced bandwidth.
Microelectron. J.
Pritty, Mansi Jhamb
2019 J jnl
A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design.
J. Circuits Syst. Comput.
Mansi Jhamb, Vinod Kumar Khera, Piyush Pant, Hinduja Pudi
2019 J jnl
Pipelined adders for ultralow-power wearables.
Turkish J. Electr. Eng. Comput. Sci.
Mansi Jhamb, Tejaswini Dhall, Tamish Verma, Hinduja Pudi
2017 J jnl
A high level implementation and performance evaluation of level-I asynchronous cache on FPGA.
J. King Saud Univ. Comput. Inf. Sci.
Mansi Jhamb, R. K. Sharma, A. K. Gupta