Manoj Sachdev - RankMe

165 papers A* 1A 24B 1C 7Misc 2Journal 69Unranked 60

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Investigating Energy Bounds of Analog Compute-in-Memory with Local Normalization. CoRR Brian Rojkov, Shubham Ranjan, Derek Wright, Manoj Sachdev
2026	J	`jnl`	Micro-display backplane power reduction techniques: Column segmentation and row charge sharing. Integr. Shubham Ranjan, Sheida Gohardehi, Manoj Sachdev
2025	J	`jnl`	Low-Power, Low-Energy, Static, Contention-Free, TSPC Dual-Edge Triggered Flip-Flops. IEEE Access Yugal Kishore Maheshwari, Manoj Sachdev
2025	J	`jnl`	VLFF - A very low-power flip-flop with only two clock transistors. Integr. Yugal Kishore Maheshwari, Manoj Sachdev
2024	—	`conf`	A Low-voltage-Driven Single-ended Column based SRAM for Low-Power Micro-display. SOCC Shubham Ranjan, Sheida Gohardehi, Manoj Sachdev
2024	J	`jnl`	A power-efficient, single-phase, contention-free flip-flop with only three clock transistors. Microelectron. J. Yugal Kishore Maheshwari, Manoj Sachdev
2024	—	`conf`	Leveraging Banking and Charge-Sharing schemes for Low-Power Micro-displays. CCECE Shubham Ranjan, Sheida Gohardehi, Manoj Sachdev
2024	J	`jnl`	Low-Power Row Driver for Digitally Driven OLEDoS Microdisplay. IEEE Trans. Circuits Syst. I Regul. Pap. Sheida Gohardehi, Manoj Sachdev
2023	J	`jnl`	Enhancing Strong PUF Security With Nonmonotonic Response Quantization. IEEE Trans. Very Large Scale Integr. Syst. Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
2023	—	`conf`	VLFF - A Very Low-power Flip-flop with only Two Clock Transistors. SOCC Yugal Kishore Maheshwari, Manoj Sachdev
2022	J	`jnl`	Design Exploration and Security Assessment of PUF-on-PUF Implementations. CoRR Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
2022	J	`jnl`	Design and Implementation of a Secure RISC-V Microprocessor. CoRR Kleber Stangherlin, Manoj Sachdev
2022	J	`jnl`	Design and Implementation of a Secure RISC-V Microprocessor. IEEE Trans. Very Large Scale Integr. Syst. Kleber Stangherlin, Manoj Sachdev
2022	J	`jnl`	Enhancing Strong PUF Security with Non-monotonic Response Quantization. CoRR Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
2022	J	`jnl`	Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR. CoRR Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
2021	J	`jnl`	Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev
2021	J	`jnl`	Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates. IEEE J. Solid State Circuits Qing Li, Czang-Ho Lee, Mohsen Asad, William S. Wong, Manoj Sachdev
2021	—	`conf`	Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization. ISQED Kleber Hugo Stangherlin, Manoj Sachdev
2021	—	`conf`	Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. ICECS Yugal Kishore Maheshwari, Kleber Stangherlin, Derek Wright, Manoj Sachdev
2020	J	`jnl`	A low-power low-offset charge-sharing technique for double-tail comparators. Microelectron. J. Ata Khorami, Roghayeh Saeidi, Manoj Sachdev
2020	—	`conf`	Accelerating STT-MRAM Ramp-up Characterization. NEWCAS Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
2020	J	`jnl`	Monitoring Aging Defects in STT-MRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
2020	—	`conf`	Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology. CICC Qing Li, Czang-Ho Lee, William S. Wong, Manoj Sachdev
2019	—	`conf`	A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications. SoCC Ata Khorami, Manoj Sachdev, Mohammad Sharifkhani
2019	J	`jnl`	A Parametric DFT Scheme for STT-MRAMs. IEEE Trans. Very Large Scale Integr. Syst. Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
2019	J	`jnl`	A low-power dynamic comparator for low-offset applications. Integr. Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani
2019	J	`jnl`	Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev
2019	A	`conf`	Strengthening PUFs using Composition. ICCAD Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara
2019	—	`conf`	Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test. SoCC Manoj Sachdev
2018	J	`jnl`	A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. IEEE J. Solid State Circuits Morteza Nabavi, Manoj Sachdev
2018	—	`conf`	An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. ISQED Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
2018	B	`conf`	Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. ETS Dhruv Patel, Derek Wright, Manoj Sachdev
2016	—	`conf`	A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. ISVLSI Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
2016	—	`conf`	Radiation hardened pulsed-latches in 65-nm CMOS. CCECE Jaspal Singh Shah, Manoj Sachdev
2015	—	`conf`	A Linear Comparator-Based Fully Digital Delay Element. ISVLSI Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev
2015	—	`conf`	A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. CICC Adam Neale, Manoj Sachdev
2015	J	`jnl`	Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs. IEEE Trans. Circuits Syst. II Express Briefs Adam Neale, Maarten Jonkman, Manoj Sachdev
2015	A	`conf`	An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). FPGA Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
2015	—	`conf`	Runtime slack-deficit detection for a low-voltage DCT circuit. MWSCAS Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
2015	C	`conf`	VLSI implementation of high-throughput, low-energy, configurable MIMO detector. ICCD Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet
2015	—	`conf`	Voltage-Boosted Synchronizers. ACM Great Lakes Symposium on VLSI Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
2014	—	`conf`	A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. CICC Adam Neale, Manoj Sachdev
2014	J	`jnl`	A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet
2014	—	`conf`	A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. SoCC Tahseen Shakir, Manoj Sachdev
2014	—	`conf`	A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications. NEWCAS Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
2014	—	`conf`	A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. CICC Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
2014	—	`conf`	Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC Manoj Sachdev, Tetsuya Iizuka
2013	—	`conf`	A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. CICC Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev
2013	J	`jnl`	An Energy-Efficient Offset-Cancelling Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs Jaspal Singh Shah, David Nairn, Manoj Sachdev
2013	J	`jnl`	Analysis and Design of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. Tasreen Charania, Ajoy Opal, Manoj Sachdev
2013	J	`jnl`	Constant Delay Logic Style. IEEE Trans. Very Large Scale Integr. Syst. Pierce Chuang, David Li, Manoj Sachdev
2012	—	`conf`	A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS. CICC Pierce Chuang, David Li, Manoj Sachdev, Vincent C. Gaudet
2012	J	`jnl`	A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs Pierce Chuang, David Li, Manoj Sachdev
2012	—	`conf`	A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. SoCC Tahseen Shakir, Manoj Sachdev
2012	C	`conf`	A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. VLSI-SoC Jaspal Singh Shah, David Nairn, Manoj Sachdev
2012	—	`conf`	A word-line boost driver design for low operating voltage 6T-SRAMs. MWSCAS Tahseen Shakir, Manoj Sachdev
2012	J	`jnl`	Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong
2012	—	`conf`	Power delivery: Droop, jitter, test and debug story (Tutorial). CICC Mike Li, Manoj Sachdev
2012	C	`conf`	Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. VLSI-SoC Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev
2011	J	`jnl`	A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Sharifkhani, Ehsan Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev
2011	—	`conf`	Analysis of power supply noise mitigation circuits. CCECE Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev
2011	—	`conf`	Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. ISQED David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev
2011	A	`conf`	Design and analysis of metastable-hardened flip-flops in sub-threshold region. ISLPED David Li, Pierce Chuang, David Nairn, Manoj Sachdev
2011	—	`conf`	Digitally programmable SRAM timing for nano-scale technologies. ISQED Adam Neale, Manoj Sachdev
2011	J	`jnl`	Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. J. Electron. Test. Muhammad Nummer, Manoj Sachdev
2011	—	`conf`	Multiprocessor FPGA implementation of a 2D digital filter. CCECE Danny Teng-Hsiang Tsuei, Mohamed-Yahia Dabbagh, Manoj Sachdev
2011	—	`conf`	Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong
2010	—	`conf`	Comparative analysis and study of metastability on high-performance flip-flops. ISQED David Li, Pierce Chuang, Manoj Sachdev
2009	J	`jnl`	A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
2009	J	`jnl`	An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
2009	J	`jnl`	An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. IEEE J. Solid State Circuits Mohammad Sharifkhani, Manoj Sachdev
2009	J	`jnl`	Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. IEEE J. Solid State Circuits Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev
2009	C	`conf`	Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic. ISCAS Pierce Chuang, David Li, Manoj Sachdev
2009	—	`conf`	ESD design challenges. CICC Manoj Sachdev, Hong-Ha Vuong
2009	—	`conf`	ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology. CICC Hossein Sarbishaei, Manoj Sachdev
2009	J	`jnl`	Low-Leakage Storage Cells for Ternary Content Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. Nitin Mohan, Manoj Sachdev
2009	J	`jnl`	SRAM Cell Stability: A Dynamic Perspective. IEEE J. Solid State Circuits Mohammad Sharifkhani, Manoj Sachdev
2008	J	`jnl`	A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. David Rennie, Manoj Sachdev
2008	C	`conf`	A fully digital ADC using a new delay element with enhanced linearity. ISCAS Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev
2008	—	`conf`	A multiword based high speed ECC scheme for low-voltage embedded SRAMS. ESSCIRC Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev
2008	—	`conf`	Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. ISQED Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
2007	C	`conf`	A Novel Tri-State Binary Phase Detector. ISCAS David Rennie, Manoj Sachdev
2007	—	`conf`	Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. ISQED David Rennie, Manoj Sachdev
2007	—	`conf`	Dynamic Data Stability in Low-power SRAM Design. CICC Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
2007	J	`jnl`	Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs. IEEE J. Solid State Circuits Nitin Mohan, Manoj Sachdev
2007	—	`conf`	Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. CICC Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev
2007	J	`jnl`	Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Sharifkhani, Manoj Sachdev
2007	J	`jnl`	Variation-Aware Adaptive Voltage Scaling System. IEEE Trans. Very Large Scale Integr. Syst. Mohamed Elgebaly, Manoj Sachdev
2006	—	`conf`	A Phase-Domain Continuous-Time 2 CICC Mohammad Sharifkhani, Manoj Sachdev
2006	A	`conf`	A low power SRAM architecture based on segmented virtual grounding. ISLPED Mohammad Sharifkhani, Manoj Sachdev
2006	C	`conf`	A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. ISCAS Mohammad Sharifkhani, Manoj Sachdev
2006	J	`jnl`	DTMOS Technique for Low-Voltage Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Maymandi-Nejad, Manoj Sachdev
2006	J	`jnl`	Design techniques and test methodology for low-power TCAMs. IEEE Trans. Very Large Scale Integr. Syst. Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
2006	—	`conf`	Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. MTDT Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
2006	—	`conf`	Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory. SoCC Nitin Mohan, Wilson Fung, Manoj Sachdev
2006	—	`conf`	Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. CICC Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
2006	J	`jnl`	New JETTA Editors, 2006. J. Electron. Test. Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
2006	—	`conf`	Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM. SoCC Nitin Mohan, Manoj Sachdev
2006	J	`jnl`	Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices. Microelectron. J. Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev
2006	—	`book`	Thermal and Power Management of Integrated Circuits Arman Vassighi, Manoj Sachdev
2006	J	`jnl`	Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
2005	—	`conf`	A 0.8V Delta-Sigma modulator using DTMOS technique. ISCAS (4) Mohammad Maymandi-Nejad, Manoj Sachdev
2005	J	`jnl`	A monotonic digitally controlled delay element. IEEE J. Solid State Circuits Mohammad Maymandi-Nejad, Manoj Sachdev
2005	—	`conf`	Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. ISQED Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev
2005	J	`jnl`	Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. Bhaskar Chatterjee, Manoj Sachdev
2005	J	`jnl`	Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2005	—	`conf`	Programmable techniques for cell stability test and debug in embedded SRAMs. CICC Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane
2005	A	`conf`	Word line pulsing technique for stability fault detection in SRAM cells. ITC Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev
2004	A	`conf`	A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2004	A	`conf`	A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. ITC Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
2004	J	`jnl`	A low-power reduced swing global clocking methodology. IEEE Trans. Very Large Scale Integr. Syst. Farhad H. A. Asgari, Manoj Sachdev
2004	A	`conf`	AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold. ITC Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
2004	—	`conf`	An Overview of Substrate Noise Reduction Techniques. ISQED Shahab Ardalan, Manoj Sachdev
2004	J	`jnl`	An analytical equation for the oscillation frequency of high-frequency ring oscillators. IEEE J. Solid State Circuits Stephen Docking, Manoj Sachdev
2004	J	`jnl`	Correction to "A Digitally Programmable Delay Element: Design and Analysis". IEEE Trans. Very Large Scale Integr. Syst. Mohammad Maymandi-Nejad, Manoj Sachdev
2004	J	`jnl`	DFT for Delay Fault Testing of High-Performance Digital Circuits. IEEE Des. Test Comput. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
2004	A*	`conf`	Design optimizations for microprocessors at low temperature. DAC Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
2004	A	`conf`	Efficient adaptive voltage scaling system through on-chip critical path emulation. ISLPED Mohamed Elgebaly, Manoj Sachdev
2004	J	`jnl`	Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET. Microelectron. Reliab. Oleg Semenov, Michael S. Obrecht, Manoj Sachdev
2004	—	`conf`	Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ISQED Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2004	—	`conf`	Low power dual matchline ternary content addressable memory. ISCAS (2) Nitin Mohan, Manoj Sachdev
2004	—	`conf`	Modeling and designing energy-delay optimized wide domino circuits. ISCAS (2) Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev
2004	J	`jnl`	The Impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness. Microelectron. Reliab. Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev
2003	J	`jnl`	A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers. J. Electron. Test. Muhammad Nummer, Manoj Sachdev
2003	J	`jnl`	A digitally programmable delay element: design and analysis. IEEE Trans. Very Large Scale Integr. Syst. Mohammad Maymandi-Nejad, Manoj Sachdev
2003	A	`conf`	Burn-in Temperature Projections for Deep Sub-micron Technologies. ITC Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins
2003	A	`conf`	DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. DATE Muhammad Nummer, Manoj Sachdev
2003	A	`conf`	Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2003	J	`jnl`	Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta J. Electron. Test. Oleg Semenov, Arman Vassighi, Manoj Sachdev
2003	J	`jnl`	Testing high-performance pipelined circuits with slow-speed testers. ACM Trans. Design Autom. Electr. Syst. Muhammad Nummer, Manoj Sachdev
2003	—	`conf`	Thermal Management of High Performance Microprocessors. DFT Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
2003	A	`conf`	Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie. ITC Derek Wright, Manoj Sachdev
2002	A	`conf`	A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. ITC Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
2002	J	`jnl`	A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. IEEE Trans. Very Large Scale Integr. Syst. Wai Chung, Timothy Lo, Manoj Sachdev
2002	—	`conf`	Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI. DFT Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
2002	J	`jnl`	Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
2002	A	`conf`	Multi-Gigahertz Digital Test Challenges and Techniques. ITC Manoj Sachdev
2002	—	`conf`	Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). ASP-DAC/VLSI Design Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta
2001	Misc	`conf`	A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency. VTS Muhammad Nummer, Manoj Sachdev
2001	A	`conf`	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
2001	J	`jnl`	Current-Based Testing for Deep-Submicron VLSIs. IEEE Des. Test Comput. Manoj Sachdev
2001	J	`jnl`	Design for Delay Testability in High-Speed Digital ICs. J. Electron. Test. Hans G. Kerkhoff, Han Speek, M. Shashani, Manoj Sachdev
2000	Misc	`conf`	A Low-Speed BIST Framework for High-Performance Circuit Testing. VTS Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
2000	—	`conf`	Bridging the testing speed gap: design for delay testability. ETW Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani
2000	A	`conf`	Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ. ITC Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De
1999	A	`conf`	A DFT technique for high performance circuit testing. ITC Mansour Shashaani, Manoj Sachdev
1999	J	`jnl`	Configurations for IDDQ-Testable PLAs. IEEE Des. Test Comput. Manoj Sachdev, Hans G. Kerkhoff
1999	J	`jnl`	Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters. J. Electron. Test. Richard Rosing, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Manoj Sachdev
1998	A	`conf`	Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs. ITC Manoj Sachdev, Peter Janssen, Victor Zieren
1997	—	`conf`	Deep sub-micron I ED&TC Manoj Sachdev
1997	J	`jnl`	Open Defects in CMOS RAM Address Decoders. IEEE Des. Test Comput. Manoj Sachdev
1996	A	`conf`	Deep Sub-micron I ITC Manoj Sachdev
1996	A	`conf`	Low power, testable dual edge triggered flip-flops. ISLPED Rafael Llopis, Manoj Sachdev
1996	J	`jnl`	Separate J. Electron. Test. Manoj Sachdev
1996	—	`conf`	Test and Testability Techniques for Open Defects in RAM Address Decoders. ED&TC Manoj Sachdev
1995	J	`jnl`	A realistic defect oriented testability methodology for analog circuits. J. Electron. Test. Manoj Sachdev
1995	—	`conf`	Defect-oriented test methodology for complex mixed-signal circuits. ED&TC F. C. M. Kuijstermans, Manoj Sachdev, A. P. Thijssen
1995	A	`conf`	I ITC Manoj Sachdev
1995	A	`conf`	Industrial Relevance of Analog IFA: A Fact or a Fiction. ITC Manoj Sachdev, Bert Atzema
1995	J	`jnl`	Reducing the CMOS RAM test complexity with J. Electron. Test. Manoj Sachdev
1995	J	`jnl`	Testing Defects in Scan Chains. IEEE Des. Test Comput. Manoj Sachdev
1994	—	`conf`	Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing. EDAC-ETC-EUROASIC Manoj Sachdev
1993	—	`conf`	Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. DFT Manoj Sachdev
1993	J	`jnl`	Comments on 'Totally self-checking CMOS circuit design for breaks and stuck-on faults'. IEEE J. Solid State Circuits Eric Bruls, Manoj Sachdev, Keith Baker
1993	A	`conf`	Development of Fault Model and Test Algorithms for Embedded DRAMs. ITC Manoj Sachdev, Math Verstraelen