Manoj Kumar Majumder

26 papers C 3Misc 1Journal 8Unranked 14

Year	Rank	Type	Title / Venue / Authors
2024	C	`conf`	Crosstalk and Power Analysis in Tapered based Composite Cu-CNT TSV in 3D IC. ISCAS Shivangi Chandrakar, Deepika Gupta, Manoj Kumar Majumder
2024	Misc	`conf`	Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA. VLSID Nidhee Bhuwal, Kamal Solanki, Manoj Kumar Majumder, Deepika Gupta
2024	C	`conf`	Implementation of Floating Charged Memristor Emulator utilizing DVCCTA. ISCAS Nidhee Bhuwal, Manoj Kumar Majumder, Deepika Gupta
2023	—	`conf`	Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack. ISQED Vandana Kumari, Maya Chandrakar, Manoj Kumar Majumder
2022	—	`conf`	Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV. VDAT Shivangi Chandrakar, Kunal Kranti Das, Deepika Gupta, Manoj Kumar Majumder
2021	J	`jnl`	Role of Through Silicon Via in 3D Integration: Impact on Delay and Power. J. Circuits Syst. Comput. Shivangi Chandrakar, Deepika Gupta, Manoj Kumar Majumder
2021	J	`jnl`	Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things. Int. J. Circuit Theory Appl. Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020	C	`conf`	A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET. ISCAS Aditya Japa, Yellappa Palagani, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
2020	J	`jnl`	Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020	J	`jnl`	Performance analysis of mixed CNT bundle interconnects at 10 nm technology. IET Circuits Devices Syst. Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
2020	—	`conf`	Signal Transmission and Reflection Losses of Cylindrical and Tapered shaped TSV in 3D Integrated Circuits. iSES Chopali Chanchal Sahu, Shivangi Chandrakar, Manoj Kumar Majumder
2020	J	`jnl`	Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2019	—	`conf`	An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits. VDAT Purvi Agrawal, Ruchi Dhamnani, Ananya Garg, Shrivishal Tripathi, Manoj Kumar Majumder
2019	—	`conf`	Designing SRAM Using CMOS and CNTFET at 32 nm Technology. iSES Arushi Shrivastava, Parul Damahe, Vijay Rao Kumbhare, Manoj Kumar Majumder
2019	—	`conf`	Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects. VDAT Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
2019	J	`jnl`	Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2018	—	`conf`	Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology. VDAT Balkrishna Choubey, Vijay Rao Kumbhare, Manoj Kumar Majumder
2015	J	`jnl`	Crosstalk Induced Delay Analysis of Randomly Distributed Mixed CNT Bundle Interconnect. J. Circuits Syst. Comput. Manoj Kumar Majumder, Pankaj Kumar Das, Vobulapuram Ramesh Kumar, Brajesh Kumar Kaushik
2014	J	`jnl`	Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects. Microelectron. Reliab. Manoj Kumar Majumder, Pankaj Kumar Das, Brajesh Kumar Kaushik
2013	—	`conf`	Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations. VDAT Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar Kaushik, Sudeb Dasgupta
2012	—	`conf`	Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects. ISQED Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
2012	—	`conf`	Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects. RAIT Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
2012	—	`conf`	Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET. VDAT Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder
2012	—	`conf`	Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. VDAT Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder
2012	—	`conf`	Novel VLSI architecture for two-dimensional radon transform computations. RAIT Baljit Kaur, Manoj Kumar Majumder
2012	—	`conf`	Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects. SocProS Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas