Manisha Pattanaik

71 papers B 1C 2Misc 4Journal 37Unranked 27

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	NOMA-Enabled UAV Trajectory Optimization Using Deep Reinforcement Learning for Efficient IoT Data Collection. IEEE Access Chaitanya Krishna Bulusu, Pragya Swami, Manisha Pattanaik, Mukesh Kumar Mishra, Tharmalingam Ratnarajah
2025	J	`jnl`	A novel spatio-topological embeddings for efficient & model-free redundant node placement in 6G IoT networks. Telecommun. Syst. Abhishek Gupta, Somesh Kumar, Manisha Pattanaik
2025	J	`jnl`	BP-IMCA: An Energy-Efficient 8T SRAM-Based Bit-Parallel In-Memory Computing Architecture. J. Circuits Syst. Comput. Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
2025	—	`conf`	Sparse Channel Estimation for Hybrid MIMO Millimeter Wave Communication Impaired by Impulsive Noise. NCC Dhruv Sanghvi, Sandesh Jain, Manisha Pattanaik, Vimal Bhatia
2024	C	`conf`	Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems. ISCAS Richa Sharma, G. K. Sharma, Manisha Pattanaik
2024	J	`jnl`	Effect of Fog Particle Size Distribution on 3D Object Detection Under Adverse Weather Conditions. CoRR Ajinkya Shinde, Gaurav Sharma, Manisha Pattanaik, Sri Niwas Singh
2024	J	`jnl`	Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors. J. Electron. Test. Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava
2024	J	`jnl`	Low-light DEtection TRansformer (LDETR): object detection in low-light and adverse weather conditions. Multim. Tools Appl. Alok Kumar Tiwari, Manisha Pattanaik, G. K. Sharma
2024	J	`jnl`	Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application. J. Electron. Test. Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava
2023	J	`jnl`	An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices. Circuits Syst. Signal Process. Anil Kumar Rajput, Alok Kumar Tiwari, Manisha Pattanaik
2023	Misc	`conf`	An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. VLSID Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
2023	J	`jnl`	Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. Microelectron. J. Anil Kumar Rajput, Manisha Pattanaik
2023	—	`conf`	Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. APCCAS Richa Sharma, G. K. Sharma, Manisha Pattanaik
2023	J	`jnl`	Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. J. Electron. Test. Richa Sharma, G. K. Sharma, Manisha Pattanaik, V. S. S. Prashant
2022	J	`jnl`	A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems. J. Electron. Test. Richa Sharma, G. K. Sharma, Manisha Pattanaik
2022	J	`jnl`	Coverage hole detection using social spider optimized Gaussian Mixture Model. J. King Saud Univ. Comput. Inf. Sci. Abhishek Gupta, Somesh Kumar, Manisha Pattanaik
2022	J	`jnl`	Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations. Microprocess. Microsystems Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
2022	J	`jnl`	Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. Microelectron. J. Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
2021	Misc	`conf`	A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. VLSID Richa Sharma, G. K. Sharma, Manisha Pattanaik
2021	J	`jnl`	A new hardware Trojan detection technique using deep convolutional neural network. Integr. Richa Sharma, Vijaypal Singh Rathor, G. K. Sharma, Manisha Pattanaik
2021	J	`jnl`	Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. IEEE Trans. Very Large Scale Integr. Syst. Neelam Arya, Manisha Pattanaik, G. K. Sharma
2021	J	`jnl`	READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency. Integr. Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
2020	—	`conf`	A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. VDAT Richa Sharma, Nitya Kritin Valivati, G. K. Sharma, Manisha Pattanaik
2020	Misc	`conf`	Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. VLSID Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
2020	J	`jnl`	Bit significance based reconfigurable approximate restoring dividers and square rooters. Microelectron. J. Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
2020	—	`conf`	Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. VDAT Anil Kumar Rajput, Manisha Pattanaik
2020	J	`jnl`	Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications. IET Circuits Devices Syst. Amit Kumar, Manisha Pattanaik, Pankaj Srivastava, Kamal Kishor Jha
2019	—	`conf`	Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. VDAT Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma
2019	—	`conf`	Semantic Image Completion and Enhancement using Deep Learning. ICCCNT Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal
2019	J	`jnl`	Semantic Image Completion and Enhancement using Deep Learning. CoRR Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal
2018	J	`jnl`	A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. Circuits Syst. Signal Process. Vikas Mahor, Manisha Pattanaik
2018	—	`conf`	Low Leakage Noise Tolerant 10T SRAM Cell. VDAT Vinay Gupta, Pratiksha Shukla, Manisha Pattanaik
2018	—	`conf`	Low Leakage Read Write Enhanced 9T SRAM Cell. VDAT Pratiksha Shukla, Vinay Gupta, Manisha Pattanaik
2017	J	`jnl`	An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. Circuits Syst. Signal Process. Vikas Mahor, Manisha Pattanaik
2017	—	`conf`	Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology. iNIS Amit Singh Rajput, Manisha Pattanaik, Ritesh Kumar Tiwari
2016	J	`jnl`	Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library. J. Circuits Syst. Comput. Vijay Kumar Sharma, Manisha Pattanaik
2016	—	`conf`	FinFET-Based Low Power Address Decoder under Process Variation. iNIS Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik
2016	—	`conf`	Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. iNIS Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik
2016	—	`conf`	Novel Ultra Low Leakage FinFET Based SRAM Cell. iNIS Vivek Kumar, Vikas Mahor, Manisha Pattanaik
2015	—	`conf`	A novel dual multiplier floating point multiply accumulate architecture. VDAT Rohit Kumar, Manisha Pattanaik
2015	J	`jnl`	A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Microelectron. Reliab. Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma
2015	J	`jnl`	Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. J. Circuits Syst. Comput. Vikas Mahor, Manisha Pattanaik
2015	J	`jnl`	New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. J. Low Power Electron. Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma
2015	J	`jnl`	Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. J. Low Power Electron. Vikas Mahor, Manisha Pattanaik
2015	—	`conf`	Performance study of side block oxide band gap engineered SONOS: A device simulation approach. VDAT Gagan Deep Verma, Manisha Pattanaik
2014	J	`jnl`	Edge preservation of impulse noise filtered images by improved anisotropic diffusion. Multim. Tools Appl. Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
2014	J	`jnl`	High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell. Wirel. Pers. Commun. Vijay Kumar Sharma, Sumit Patel, Manisha Pattanaik
2014	—	`conf`	NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. NANOARCH Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma
2014	—	`conf`	Operation-aware assist circuit design for improved write performance of FinFET based SRAM. VDAT Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma
2014	J	`jnl`	PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron. Reliab. Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj
2014	J	`jnl`	Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. Microelectron. J. Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik
2014	J	`jnl`	Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits. J. Low Power Electron. Vijay Kumar Sharma, Manisha Pattanaik
2014	—	`conf`	TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach. VDAT Shipra Bassi, Manisha Pattanaik
2014	J	`jnl`	Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study. J. Circuits Syst. Comput. Vijay Kumar Sharma, Manisha Pattanaik
2013	—	`conf`	Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. ECCTD Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik, G. K. Sharma
2013	J	`jnl`	Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement. Signal Process. Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
2012	—	`conf`	A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell. ISED Santhosh Keshavarapu, Saumya Jain, Manisha Pattanaik
2012	—	`conf`	A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. ISED Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik
2012	—	`conf`	Fuzzy based diffusion coefficient function in anisotropic diffusion for impulse noise removal. ICVGIP Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
2012	—	`conf`	Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. ISED Shashikant Sharma, Manisha Pattanaik, Balwinder Raj
2011	—	`conf`	A New Adaptive Thresholding in SVD for Efficient Image De-noising. SocProS (2) Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
2011	—	`conf`	A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor
2011	J	`jnl`	Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. VLSI Design Subhra Dhar, Manisha Pattanaik, Poolla Rajaram
2011	—	`conf`	An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. ISVLSI Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik
2011	J	`jnl`	Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology. Circuits Syst. Shilpi Birla, Neeraj Kumar Shukla, Kapil Rathi, Rakesh Kumar Singh, Manisha Pattanaik
2011	J	`jnl`	Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications. Circuits Syst. Shilpi Birla, Rakesh Kumar Singh, Manisha Pattanaik
2010	—	`conf`	An Efficient Compressed Domain Spatial Transcoding Scheme for Adaptive Video Content Delivery. PCM (2) Nishant Khanwalkar, Shashikala Tapaswi, Manisha Pattanaik
2010	B	`conf`	An efficient image noise removal and enhancement method. SMC Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
2010	C	`conf`	Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. DSD Deepak Kumar, Pankaj Kumar, Manisha Pattanaik
2010	—	`conf`	Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design. SBCCI Deepak Kumar, Pankaj Kumar, Manisha Pattanaik
2003	Misc	`conf`	A New Approach to Analyze a Sub-micron CMOS Inverter. VLSI Design Manisha Pattanaik, Swapna Banerjee