Manish Kumar Jaiswal

30 papers A 1B 1C 2Misc 2Journal 13Unranked 11

Year	Rank	Type	Title / Venue / Authors
2019	J	`jnl`	Design of quadruple precision multiplier architectures with SIMD single and double precision support. Integr. Manish Kumar Jaiswal, Hayden Kwok-Hay So
2019	J	`jnl`	PACoGen: A Hardware Posit Arithmetic Core Generator. IEEE Access Manish Kumar Jaiswal, Hayden Kwok-Hay So
2018	J	`jnl`	An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division. Circuits Syst. Signal Process. Manish Kumar Jaiswal, Hayden Kwok-Hay So
2018	C	`conf`	Architecture Generator for Type-3 Unum Posit Adder/Subtractor. ISCAS Manish Kumar Jaiswal, Hayden Kwok-Hay So
2018	J	`jnl`	Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA. IEEE Embed. Syst. Lett. Farkhanda Syed, Zahid Ullah, Manish Kumar Jaiswal
2018	A	`conf`	Universal number posit arithmetic generator on FPGA. DATE Manish Kumar Jaiswal, Hayden Kwok-Hay So
2017	J	`jnl`	Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division. IEEE Trans. Circuits Syst. I Regul. Pap. Manish Kumar Jaiswal, Hayden Kwok-Hay So
2016	—	`conf`	Architecture for quadruple precision floating point division with multi-precision support. ASAP Manish Kumar Jaiswal, Hayden Kwok-Hay So
2016	—	`conf`	Dual-mode double precision division architecture. MWSCAS Manish Kumar Jaiswal, Hayden Kwok-Hay So
2016	—	`conf`	High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform. ReConFig Ho-Cheung Ng, Maolin Wang, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Sam M. H. Ho, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
2016	—	`conf`	Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. FPT Maolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So
2016	—	`conf`	Taylor Series Based Architecture for Quadruple Precision Floating Point Division. ISVLSI Manish Kumar Jaiswal, Hayden Kwok-Hay So
2015	—	`conf`	Architecture for Dual-Mode Quadruple Precision Floating Point Adder. ISVLSI Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So
2015	J	`jnl`	Configurable Architectures for Multi-Mode Floating Point Adders. IEEE Trans. Circuits Syst. I Regul. Pap. Manish Kumar Jaiswal, B. Sharat Chandra Varma, Hayden Kwok-Hay So, M. Balakrishnan, Kolin Paul, Ray C. C. Cheung
2015	C	`conf`	Dual-mode double precision / two-parallel single precision floating point multiplier architecture. VLSI-SoC Manish Kumar Jaiswal, Hayden Kwok-Hay So
2015	J	`jnl`	Z-TCAM: An SRAM-based Architecture for TCAM. IEEE Trans. Very Large Scale Integr. Syst. Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
2014	—	`conf`	Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division. ISVLSI Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2014	J	`jnl`	E-TCAM: An Efficient SRAM-Based Architecture for TCAM. Circuits Syst. Signal Process. Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
2014	J	`jnl`	Series Expansion based Efficient Architectures for Double Precision Floating Point Division. Circuits Syst. Signal Process. Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2014	J	`jnl`	Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder. IEEE Trans. Circuits Syst. II Express Briefs Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul
2013	J	`jnl`	Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support. Microelectron. J. Manish Kumar Jaiswal, Ray C. C. Cheung
2013	B	`conf`	Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM). FPL Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung
2013	J	`jnl`	VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique. Circuits Syst. Signal Process. Manish Kumar Jaiswal, Ray C. C. Cheung
2012	Misc	`conf`	Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers. FCCM Manish Kumar Jaiswal, Ray C. C. Cheung
2012	—	`conf`	Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier. IPDPS Workshops Manish Kumar Jaiswal, Ray C. C. Cheung
2012	—	`conf`	FPGA Implementation of SRAM-based Ternary Content Addressable Memory. IPDPS Workshops Zahid Ullah, Manish Kumar Jaiswal, Y. C. Chan, Ray C. C. Cheung
2012	J	`jnl`	FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture. IEEE Trans. Computers Manish Kumar Jaiswal, Nitin Chandrachoodan
2012	—	`conf`	High Performance Reconfigurable Architecture for Double Precision Floating Point Division. ARC Manish Kumar Jaiswal, Ray C. C. Cheung
2009	Misc	`conf`	Efficient Implementation of Floating-Point Reciprocator on FPGA. VLSI Design Manish Kumar Jaiswal, Nitin Chandrachoodan
2008	—	`conf`	Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA. ICIIS Manish Kumar Jaiswal, Nitin Chandrachoodan