Mango Chia-Tso Chao

63 papers A* 3A 21C 2Misc 15Journal 13Unranked 9

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	COPA: A Congestion-Oriented Pin Assignment Framework for Intra-Block Physical Design Optimization. ICCAD Shu-Yi Tsai, Yu-Guang Chen, Kun-Min Chen, Sheng-Bing Ke, Chung-Hui Hsieh, Chih-Wei Lin, Mango Chia-Tso Chao
2025	—	`conf`	Overcoming Training Data Scarcity in Routing Demand Prediction via Ensemble Learning. ACM Great Lakes Symposium on VLSI Yu-Guang Chen, Shih-Cheng Huang, Cheng-Hong Tsai, De-Shiun Fu, Mango Chia-Tso Chao
2025	Misc	`conf`	Test Methodology for Detecting Defect-Based Hold-Time Faults. VTS Cheng-Hsiang Tsai, Yu-Teng Nien, Guan-You Chen, Mango Chia-Tso Chao
2024	—	`conf`	IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization. ISOCC Yu-Guang Chen, Hung-Han Chang, Yu-Chuan Liang, Wen-Hsiang Chang, I-Ching Tsai, Chih-Wei Lin, Yun-Chih Chang, Mango Chia-Tso Chao
2024	Misc	`conf`	Transformer and Its Variants for Identifying Good Dice in Bad Neighborhoods. VTS Cheng-Che Lu, Chi-Chih Chang, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
2024	A	`conf`	Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant. ITC Shu-Wen Li, Chia-Heng Yen, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
2023	J	`jnl`	CNN-Based Stochastic Regression for IDDQ Outlier Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chia-Heng Yen, Chun-Teng Chen, Cheng-Yen Wen, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
2023	J	`jnl`	DRC Violation Prediction After Global Route Through Convolutional Neural Network. IEEE Trans. Very Large Scale Integr. Syst. Wei-Tse Hung, Yu-Guang Chen, Jhen-Gang Lin, Yun-Wei Yang, Cheng-Hong Tsai, Mango Chia-Tso Chao
2023	—	`conf`	DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. ACM Great Lakes Symposium on VLSI Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu, Mango Chia-Tso Chao
2023	A	`conf`	Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. ITC Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao
2023	Misc	`conf`	Outlier Detection for Analog Tests Using Deep Learning Techniques. VTS Chin-Kuan Lin, Cheng-Che Lu, Shuo-Wen Chang, Ying-Hua Chu, Kai-Chiang Wu, Mango Chia-Tso Chao
2022	J	`jnl`	Methodology of Generating Timing-Slack-Based Cell-Aware Tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2021	Misc	`conf`	Identifying Good-Dice-in-Bad-Neighborhoods Using Artificial Neural Networks. VTS Cheng-Hao Yang, Chia-Heng Yen, Ting-Rui Wang, Chun-Teng Chen, Mason Chern, Ying-Yen Chen, Jih-Nung Lee, Shu-Yi Kao, Kai-Chiang Wu, Mango Chia-Tso Chao
2020	Misc	`conf`	CNN-based Stochastic Regression for IDDQ Outlier Identification. VTS Chun-Teng Chen, Chia-Heng Yen, Cheng-Yen Wen, Cheng-Hao Yang, Kai-Chiang Wu, Mason Chern, Ying-Yen Chen, Chun-Yi Kuo, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2020	—	`conf`	Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. ISPD Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, Mango Chia-Tso Chao
2019	A	`conf`	Methodology of Generating Timing-Slack-Based Cell-Aware Tests. ITC Yu-Teng Nien, Kai-Chiang Wu, Dong-Zhen Lee, Ying-Yen Chen, Po-Lin Chen, Mason Chern, Jih-Nung Lee, Shu-Yi Kao, Mango Chia-Tso Chao
2019	—	`conf`	Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. VLSI-DAT Yu-Zhe Wang, Jingjie Wu, Shi-Hao Chen, Mango Chia-Tso Chao, Chia-Hsiang Yang
2017	Misc	`conf`	Fast WAT test structure for measuring Vt variance based on latch-based comparators. VTS Kao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao
2016	—	`conf`	Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique. ISPD Wen-Hsiang Chang, Li-De Chen, Chien-Hsueh Lin, Szu-Pang Mu, Mango Chia-Tso Chao, Cheng-Hong Tsai, Yen-Chih Chiu
2015	Misc	`conf`	Random pattern generation for post-silicon validation of DDR3 SDRAM. VTS Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao
2015	Misc	`conf`	Statistical techniques for predicting system-level failure using stress-test data. VTS Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao
2015	A	`conf`	Testing methods for quaternary content addressable memory using charge-sharing sensing scheme. ITC Hao-Yu Yang, Rei-Fu Huang, Chin-Lung Su, Kuan-Hong Lin, Hang-Kaung Shu, Chi-Wei Peng, Mango Chia-Tso Chao
2014	J	`jnl`	Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization. IEEE Trans. Very Large Scale Integr. Syst. Tseng-Chin Luo, Mango Chia-Tso Chao, Huan-Chi Tseng, Masaharu Goto, Philip A. Fisher, Yuan-Yao Chang, Chi-Min Chang, Takayuki Takao, Katsuhito Iwasaki, Cheng Mao Lee
2014	J	`jnl`	Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu
2014	—	`conf`	Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs. VLSI-DAT Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li
2014	J	`jnl`	Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer. IEEE Trans. Very Large Scale Integr. Syst. Wen-Hsiang Chang, Mango Chia-Tso Chao, Shi-Hao Chen
2014	Misc	`conf`	Testing methods for a write-assist disturbance-free dual-port SRAM. VTS Hao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang
2013	J	`jnl`	Fault Models and Test Methods for Subthreshold SRAMs. IEEE Trans. Computers Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Chin-Yuan Huang, Mango Chia-Tso Chao, Rei-Fu Huang
2013	Misc	`conf`	Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs. VTS Chen-Wei Lin, Mango Chia-Tso Chao, Chih-Chieh Hsu
2013	J	`jnl`	Power-Up Sequence Control for MTCMOS Designs. IEEE Trans. Very Large Scale Integr. Syst. Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao
2013	Misc	`conf`	Testing of a low-VMIN data-aware dynamic-supply 8T SRAM. VTS Chen-Wei Lin, Chin-Yuan Huang, Mango Chia-Tso Chao
2013	Misc	`conf`	Testing retention flip-flops in power-gated designs. VTS Hao-Wen Hsu, Shih-Hua Kuo, Wen-Hsiang Chang, Shi-Hao Chen, Ming-Tung Chang, Mango Chia-Tso Chao
2012	A*	`conf`	Alternate hammering test for application-specific DRAMs and an industrial case study. DAC Rei-Fu Huang, Hao-Yu Yang, Mango Chia-Tso Chao, Shih-Chin Lin
2012	—	`conf`	An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs. ASP-DAC Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao
2012	J	`jnl`	Testing Methodology of Embedded DRAMs. IEEE Trans. Very Large Scale Integr. Syst. Hao-Yu Yang, Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Shih-Chin Lin
2012	A	`conf`	Testing strategies for a 9T sub-threshold SRAM. ITC Hao-Yu Yang, Chen-Wei Lin, Hung-Hsin Chen, Mango Chia-Tso Chao, Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang
2011	J	`jnl`	A Novel Test Flow for One-Time-Programming Applications of NROM Technology. IEEE Trans. Very Large Scale Integr. Syst. Mango Chia-Tso Chao, Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang
2011	A	`conf`	Design-for-debug layout adjustment for FIB probing and circuit editing. ITC Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen
2011	A	`conf`	Detecting stability faults in sub-threshold SRAMs. ICCAD Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao
2010	J	`jnl`	A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang
2010	A	`conf`	Fault models and test methods for subthreshold SRAMs. ITC Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang
2010	A	`conf`	Mask versus Schematic - an enhanced design-verification flow for first silicon success. ITC Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang
2010	A	`conf`	Mathematical yield estimation for two-dimensional-redundancy memory arrays. ICCAD Mango Chia-Tso Chao, Ching-Yu Chin, Chen-Wei Lin
2010	J	`jnl`	Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes. ACM Trans. Design Autom. Electr. Syst. Yu-Ze Wu, Mango Chia-Tso Chao
2010	A	`conf`	Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs. ICCAD Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai
2010	Misc	`conf`	Theoretical analysis for low-power test decompression using test-slice duplication. VTS Szu-Pang Mu, Mango Chia-Tso Chao
2009	—	`conf`	A metal-only-ECO solver for input-slew and output-loading violations. ISPD Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang
2009	A	`conf`	A novel array-based test methodology for local process variation monitoring. ITC Tseng-Chin Luo, Mango Chia-Tso Chao, Michael S.-Y. Wu, Kuo-Tsai Li, Chin C. Hsia, Huan-Chi Tseng, Chuen-Uan Huang, Yuan-Yao Chang, Samuel C. Pan, Konrad K.-L. Young
2009	A	`conf`	A novel test flow for one-time-programming applications of NROM technology. ITC Ching-Yu Chin, Yao-Te Tsou, Chi-Min Chang, Mango Chia-Tso Chao
2009	A*	`conf`	Fault models for embedded-DRAM macros. DAC Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin
2009	Misc	`conf`	Multiple-Fault Diagnosis Using Faulty-Region Identification. VTS Meng-Jai Tasi, Mango Chia-Tso Chao, Jing-Yang Jou, Meng-Chen Wu
2009	A	`conf`	Power-switch routing for coarse-grain MTCMOS technologies. ICCAD Tsun-Ming Tseng, Mango Chia-Tso Chao, Chien Pang Lu, Chen Hsing Lo
2008	Misc	`conf`	Scan-Chain Reordering for Minimizing Scan-Shift Power Based on Non-Specified Test Cubes. VTS Yu-Ze Wu, Mango Chia-Tso Chao
2008	A	`conf`	Testing Methodology of Embedded DRAMs. ITC Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen
2007	A	`conf`	A hybrid scheme for compacting test responses with unknown values. ICCAD Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei
2006	A	`conf`	Coverage loss by using space compactors in presence of unknown values. DATE Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei, Kwang-Ting Cheng
2006	A*	`conf`	Unknown-tolerance analysis and test-quality control for test response compaction using space compactors. DAC Mango Chia-Tso Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wenlong Wei
2005	C	`conf`	ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values. ICCD Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
2005	A	`conf`	Response shaper: a novel technique to enhance unknown tolerance for output response compaction. ICCAD Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng
2004	J	`jnl`	A clustering- and probability-based approach for time-multiplexed FPGA partitioning. Integr. Guang-Ming Wu, Mango Chia-Tso Chao, Yao-Wen Chang
2004	A	`conf`	Pattern Selection for Testing of Deep Sub-Micron Timing Defects. DATE Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
2001	C	`conf`	Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
1999	A	`conf`	A clustering- and probability-based approach for time-multiplexed FPGA partitioning. ICCAD Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang