Manfred Glesner

360 papers A* 7A 20B 50C 48Misc 14Journal 49Unranked 166

Year	Rank	Type	Title / Venue / Authors
2017	—	`conf`	VLSI-SoC: An Enduring Tradition. VLSI-SoC (Selected Papers) Ricardo Reis, Manfred Glesner
2014	—	`conf`	High-level abstraction for teaching smart systems design with modular hardware. EWME François Philipp, Manfred Glesner
2013	B	`conf`	An event-based middleware for the remote management of runtime hardware reconfiguration. FPL François Philipp, Manfred Glesner
2013	—	`conf`	Design of an organic electronic label on a flexible substrate for temperature sensing. ESSCIRC Ramkumar Ganesan, Jürgen Krumm, Sebastian Pankalla, Klaus Ludwig, Manfred Glesner
2013	—	`conf`	Embedded systems design for smart system integration. ISVLSI Manfred Glesner, François Philipp
2013	J	`jnl`	Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach. ACM Trans. Embed. Comput. Syst. Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Möller, Leandro Soares Indrusiak, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert, Fernando Moraes
2013	J	`jnl`	Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2012	B	`conf`	(GECO) FPL François Philipp, Manfred Glesner
2012	J	`jnl`	A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme. Int. J. Reconfigurable Comput. Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak, Weiler Alves Finamore, Manfred Glesner
2012	—	`conf`	Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs. ISSoC Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Fernando Gehm Moraes, Manfred Glesner
2012	J	`jnl`	Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461. Microprocess. Microsystems Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2012	—	`conf`	Hardware acceleration of combined cipher and forward error correction for low-power wireless applications. ReCoSoC François Philipp, Conrad Klytta, Manfred Glesner, Élvio Dutra
2012	B	`conf`	Implementation and outcomes of FPGA-based system design in Mongolian education. FPL D. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner
2012	J	`jnl`	Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method. Microprocess. Microsystems Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2011	—	`conf`	A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit. IPDPS Workshops François Philipp, Manfred Glesner
2011	C	`conf`	Design of an autonomous platform for distributed sensing-actuating systems. International Symposium on Rapid System Prototyping François Philipp, Faizal Arya Samman, Manfred Glesner
2011	—	`conf`	Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework. SBCCI Luciano Ost, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Soares Indrusiak, Leandro Möller, Manfred Glesner, Gilles Sassatelli, Michel Robert, Fernando Moraes
2011	—	`conf`	Invited paper: Design criteria for dependable System-on-Chip architectures. ReCoSoC Thomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann
2011	B	`conf`	Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node. FPL François Philipp, Manfred Glesner
2011	J	`jnl`	New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2011	C	`conf`	On-chip efficient Round-Robin scheduler for high-speed interconnection. International Symposium on Rapid System Prototyping Surapong Pongyupinpanich, Manfred Glesner
2011	B	`conf`	Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC. FPL Surapong Pongyupinpanich, Manfred Glesner
2011	C	`conf`	RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier. ISCAS Ping Zhao, Manfred Glesner
2011	—	`conf`	Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems. CHANGE@ASPLOS Faizal Arya Samman, François Philipp, Manfred Glesner
2011	—	`conf`	Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems. ReCoSoC Faizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner
2011	J	`jnl`	Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip. Microprocess. Microsystems Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2010	—	`conf`	A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II. SoC Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi
2010	J	`jnl`	Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2010	—	`ch.`	Dynamically Reconfigurable Systems for Wireless Sensor Networks. Dynamically Reconfigurable Systems Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2010	B	`conf`	Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. FPL Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
2010	—	`conf`	Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. ReCoSoC Leandro Möller, André Rodrigues, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner
2010	J	`jnl`	Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms. Int. J. Embed. Real Time Commun. Syst. Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes
2010	—	`conf`	Novel method of chaotic systems evaluation for implementations of encryption algorithms. ICT Élvio Dutra, Manfred Glesner, Weiler Alves Finamore, Leandro Soares Indrusiak
2009	J	`jnl`	A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. Int. J. Reconfigurable Comput. Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner
2009	C	`conf`	A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures. VLSI-SoC Petru Bogdan Bacinschi, Manfred Glesner
2009	A	`conf`	A flexible floating-point wavelet transform and wavelet packet processor. DATE Andre Guntoro, Manfred Glesner
2009	B	`conf`	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009	—	`conf`	Characterising embedded applications using a UML profile. SoC Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes, Jari Nurmi
2009	B	`conf`	Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. FPL Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2009	A	`conf`	Generation of Synthetic Floating-Point benchmark circuits. IPDPS Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner
2009	J	`jnl`	Low-Power Coding for Networks-on-Chip with Virtual Channels. J. Low Power Electron. Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
2009	J	`jnl`	Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management. VLSI Design Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2009	J	`jnl`	On the design of reconfigurable multipliers for integer and Galois field multiplication. Microprocess. Microsystems Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner
2009	J	`jnl`	Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms. Int. J. Reconfigurable Comput. Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner
2009	B	`conf`	Towards a unique FPGA-based identification circuit using process variations. FPL Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
2008	—	`conf`	A Flexible Floating-Point Wavelet Processor. SITIS Andre Guntoro, Manfred Glesner
2008	—	`conf`	A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters. VLSI-SoC (Selected Papers) Andre Guntoro, Manfred Glesner
2008	C	`conf`	A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. IEEE International Workshop on Rapid System Prototyping Heiko Hinkelmann, Andreas Reinhardt, Manfred Glesner
2008	J	`jnl`	A fast and compact classifier based on sorting in an iteratively expanded input space. Int. J. Intell. Syst. Radu Dogaru, Manfred Glesner
2008	B	`conf`	A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. FPL Andre Guntoro, Manfred Glesner
2008	—	`conf`	A novel leakage-estimation method for input-vector control. APCCAS Hans-Peter Keil, Massoud Momeni, Andre Guntoro, Alberto García Ortiz, Manfred Glesner
2008	—	`conf`	A scalable reconfiguration mechanism for fast dynamic reconfiguration. FPT Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	—	`conf`	A simplified executable model to evaluate latency and throughput of networks-on-chip. SBCCI Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi
2008	—	`conf`	An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks. ICDCS Workshops Enkhbold Ochirsuren, Leandro Soares Indrusiak, Manfred Glesner
2008	A	`conf`	An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. DATE Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner
2008	—	`conf`	An area-efficient FPGA realisation of a codebook-based image compression method. FPT Peter Zipf, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner
2008	B	`conf`	Application-specific reconfigurable processors. FPL Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll
2008	—	`conf`	Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. ISVLSI Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner
2008	C	`conf`	Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. IEEE International Workshop on Rapid System Prototyping Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil
2008	B	`conf`	Coarse-grained reconfiguration. FPL Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2008	A	`conf`	Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. DATE Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner
2008	—	`conf`	Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor. SIGMAP Andre Guntoro, Hans-Peter Keil, Manfred Glesner
2008	—	`conf`	Enabling self-reconfiguration on a video processing platform. SIES Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner
2008	A	`conf`	Flexible parallel pipeline network-on-chip based on dynamic packet identity management. IPDPS Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2008	—	`ch.`	Hardware Based Rapid Prototyping. Wiley Encyclopedia of Computer Science and Engineering Manfred Glesner, Tudor Murgan, Thomas Hollstein
2008	—	`conf`	High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor. ICETE (Selected Papers) Andre Guntoro, Hans-Peter Keil, Manfred Glesner
2008	—	`conf`	High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms. APCCAS Andre Guntoro, Massoud Momeni, Hans-Peter Keil, Manfred Glesner
2008	B	`conf`	High-performance fpga-based floating-point adder with three inputs. FPL Andre Guntoro, Manfred Glesner
2008	—	`conf`	Impact of circuit nonidealities on the implementation of switched-capacitor resonators. APCCAS Massoud Momeni, Andre Guntoro, Hans-Peter Keil, Manfred Glesner
2008	—	`conf`	Low-latency VLSI architecture of a 3-input floating-point adder. APCCAS Andre Guntoro, Manfred Glesner
2008	A	`conf`	Multicast Parallel Pipeline Router Architecture for Network-on-Chip. DATE Faizal Arya Samman, Thomas Hollstein, Manfred Glesner
2008	—	`conf`	Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. ASAP Andre Guntoro, Manfred Glesner
2008	—	`conf`	PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. PATMOS Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
2008	C	`conf`	Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner
2008	—	`conf`	TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor. DIPES Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner
2008	—	`conf`	Validation of executable application models mapped onto network-on-chip platforms. SIES Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes
2007	—	`conf`	A Customizable LEON2-Based VLIW Processor. ReCoSoC Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner
2007	—	`conf`	A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. FPT Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2007	B	`conf`	A Power Estimation Model for an FPGA-based Softcore Processor. FPL Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll
2007	B	`conf`	A Scalable Resampling Architecture. GLOBECOM Mihail Petrov, Manfred Glesner
2007	J	`jnl`	Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. Comput. Electr. Eng. Thomas Hollstein, Manfred Glesner
2007	B	`conf`	An Efficient Fractional-Rate Interpolation Architecture. GLOBECOM Mihail Petrov, Manfred Glesner
2007	J	`jnl`	Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck
2007	—	`conf`	Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. MBMV Peter Zipf, Yang Qiao, Manfred Glesner
2007	—	`conf`	Inserting Data Encoding Techniques into NoC-Based Systems. ISVLSI José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2007	A	`conf`	Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. DATE Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner
2007	—	`conf`	Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. ReCoSoC Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner
2007	—	`conf`	On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner
2007	J	`jnl`	On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems. IEEE Trans. Ind. Electron. Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis
2007	—	`conf`	On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
2007	—	`ed.`	Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007 ReCoSoC Gilles Sassatelli, Manfred Glesner, Christophe Bobda, Pascal Benoit
2007	—	`conf`	Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes. ICECS José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Ricardo Reis, Manfred Glesner
2007	J	`jnl`	Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems. J. Low Power Electron. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2007	J	`jnl`	Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. Sujan Pandey, Manfred Glesner
2007	—	`conf`	Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models. SBCCI Leandro Soares Indrusiak, Manfred Glesner
2007	—	`conf`	System Level Design of a Dynamically Self-Reconfigurable Image Processing System. ReCoSoC Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. PATMOS Clemens Schlachta, Manfred Glesner
2006	—	`conf`	A Concept for a Profile-based Dynamic Reconfiguration Mechanism. ReCoSoC Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	A	`conf`	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. ICCAD Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
2006	—	`conf`	A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	A	`conf`	A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. DATE Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner
2006	—	`conf`	Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations. ReCoSoC Kurt Franz Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. PATMOS José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2006	—	`conf`	An Actor-Oriented Model-Based Design Flow for Systems-on-Chip. MBEES Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. ISVLSI Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner
2006	C	`conf`	Applying Communication Patterns to Actor-Oriented Models. FDL Andreas Thuy, Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. AHS Heiko Hinkelmann, Peter Zipf, Manfred Glesner
2006	—	`conf`	Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck
2006	C	`conf`	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC Sujan Pandey, Tudor Murgan, Manfred Glesner
2006	B	`conf`	Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL Sujan Pandey, Manfred Glesner
2006	C	`conf`	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS Sujan Pandey, Manfred Glesner
2006	—	`conf`	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. ISVLSI José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
2006	—	`conf`	Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms. ReCoSoC Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner
2006	—	`conf`	Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner
2006	B	`conf`	Multitasking Support for Dynamically Reconfig Urable Systems. FPL Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner
2006	—	`conf`	Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. PATMOS Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner
2006	—	`ed.`	Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006 ReCoSoC Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres
2006	C	`conf`	Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier
2006	C	`conf`	Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner
2006	A*	`conf`	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC Sujan Pandey, Manfred Glesner
2006	C	`conf`	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC Sujan Pandey, Nurten Utlu, Manfred Glesner
2006	—	`conf`	Towards an Automated Design of Application-specific Reconfigurable Logic. Dynamically Reconfigurable Architectures Peter Zipf, Manfred Glesner
2006	—	`ed.`	VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany VLSI-SoC (Selected Papers) Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak, Vincent John Mooney III, Hans Eveking
2005	B	`conf`	A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. FPL Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner
2005	—	`conf`	A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA. FPT Mihail Petrov, Manfred Glesner
2005	—	`conf`	A linear model for high-level delay estimation in VDSM on-chip interconnects. ISCAS (2) Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
2005	—	`conf`	Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. GI Jahrestagung (1) Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner
2005	—	`conf`	Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC Thomas Hollstein, Sujan Pandey, Manfred Glesner
2005	J	`jnl`	An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation. Microelectron. J. Cristian Chitu, Manfred Glesner
2005	—	`conf`	Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. ReCoSoC Peter Zipf, Claude Stötzler, Manfred Glesner
2005	A	`conf`	Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip. IPDPS Heiko Zimmer, Stefan Zink, Thomas Hollstein, Manfred Glesner
2005	—	`conf`	CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, Antonio Rubio
2005	A	`conf`	Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. ICCAD Martin K. F. Schafer, Thomas Hollstein, Heiko Zimmer, Manfred Glesner
2005	—	`conf`	Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. ReCoSoC Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel
2005	—	`conf`	Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. GI Jahrestagung (1) Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner
2005	—	`conf`	Experiences on Actor-oriented Design of Reconfigurable Systems. ReCoSoC Leandro Soares Indrusiak, Manfred Glesner
2005	—	`conf`	Functional modeling techniques for a wireless LAN OFDM transceiver. ISCAS (4) A. Petrov, Tudor Murgan, Peter Zipf, Manfred Glesner
2005	—	`conf`	HW/SW design and realization of a size-reconfigurable DCT accelerator. ICECS Abdulfattah Mohammad Obeid, Tudor Murgan, Abdelouahid Taadou, Manfred Glesner
2005	—	`conf`	High level hardware/software communication estimation in shared memory architecture. ISCAS (1) Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
2005	C	`conf`	Modeling and Prototyping of Communication Systems Using Java: A Case Study. IEEE International Workshop on Rapid System Prototyping Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner
2005	—	`conf`	Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. SBCCI Élvio Dutra, Leandro Soares Indrusiak, Manfred Glesner
2005	C	`conf`	On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. VLSI-SoC Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
2005	B	`conf`	On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL Sujan Pandey, Manfred Glesner, Max Mühlhäuser
2005	—	`conf`	Optimal FFT Architecture Selection for OFDM Receivers on FPGA. FPT Mihail Petrov, Manfred Glesner
2005	—	`conf`	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI Sujan Pandey, Manfred Glesner, Max Mühlhäuser
2005	—	`ed.`	Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005 ReCoSoC Gilles Sassatelli, Manfred Glesner, Lionel Torres, Leandro Soares Indrusiak, Thomas Hollstein
2005	B	`conf`	Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. FPL Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner
2005	—	`conf`	Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics. MSE Diego Fernando Jimenez Orostegui, Leandro Soares Indrusiak, Manfred Glesner
2005	—	`conf`	Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. ARCS Workshops Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner
2005	—	`conf`	Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
2004	—	`conf`	A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ISVLSI Peter Zipf, Claude Stötzler, Manfred Glesner
2004	B	`conf`	A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. FPL Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner
2004	J	`jnl`	A power-constrained design strategy for CMOS tuned low noise amplifiers. Microelectron. Reliab. Oliver Mitea, Manfred Glesner
2004	—	`conf`	A switch architecture and signal synchronization for GALS system-on-chips. SBCCI Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner
2004	—	`conf`	Accurate capture of timing parameters in inductively-coupled on-chip interconnects. SBCCI Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2004	—	`conf`	Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner
2004	—	`conf`	An Asynchronous Switch Implmentation for Systems-on-a-Chip. MBMV Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner
2004	B	`conf`	CPCA: a multiplierless neural PCA. IJCNN Radu Dogaru, Ioana Dogaru, Manfred Glesner
2004	—	`conf`	Design of a reconfigurable AES encryption/decryption engine for mobile terminals. ISCAS (2) Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004	—	`conf`	Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
2004	—	`conf`	Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel
2004	B	`conf`	IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. FPL Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
2004	—	`conf`	Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. ARCS Workshops Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner
2004	—	`conf`	Lookup-based Remote Laboratory for FPGA Digital Design Prototyping. VIRTUAL-LAB Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
2004	—	`conf`	Moment-Based Estimation of Switching Activity for Correlated Distributions. PATMOS Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2004	—	`conf`	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. PATMOS Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner
2004	A	`conf`	On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. FPGA Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner
2004	C	`conf`	Rapid Prototyping of an Integrated Testing and Debugging Unit. IEEE International Workshop on Rapid System Prototyping Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner
2004	—	`conf`	Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan
2004	B	`conf`	The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner
2004	J	`jnl`	Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados. RITA Leandro Soares Indrusiak, Ricardo A. L. Reis, Manfred Glesner
2003	C	`conf`	A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications. VLSI-SOC Radu Dogaru, Cristian Chitu, Manfred Glesner
2003	A	`conf`	A granularity-based classification model for systems-on-a-chip. FPGA Stephan Bingemer, Peter Zipf, Manfred Glesner
2003	C	`conf`	A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
2003	—	`conf`	A linearization technique for radio frequency CMOS Gilbert-type mixers. ICECS Octavian Mitrea, Cosmin Popa, Anca Manuela Manolescu, Manfred Glesner
2003	—	`conf`	A low-IF architecture for dual-standard GSM/UMTS fully integrated receivers. ICECS Octavian Mitrea, Juan Jesús Ocampo Hidalgo, Manfred Glesner
2003	—	`conf`	A multi-path high speed Viterbi decoder. ICECS Abdulfattah Mohammad Obeid, Alberto García Ortiz, Mihail Petrov, Manfred Glesner
2003	C	`conf`	An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
2003	C	`conf`	An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC Stephan Bingemer, Peter Zipf, Manfred Glesner
2003	—	`conf`	Arbitrary function approximation in HDLs with application to the N-body problem. FPT Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2003	—	`conf`	Compact image compression using simplicial and ART neural systems with mixed signal implementations. ISCAS (5) Radu Dogaru, Ioana Dogaru, Manfred Glesner
2003	C	`conf`	Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. IEEE International Workshop on Rapid System Prototyping Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesús Ocampo Hidalgo, Manfred Glesner
2003	B	`conf`	Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
2003	—	`conf`	Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans. VLSI-SoC (Selected Papers) Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	C	`conf`	Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. VLSI-SOC Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	J	`jnl`	Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems. Des. Autom. Embed. Syst. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2003	C	`conf`	High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation. VLSI-SOC Cristian Chitu, Manfred Glesner
2003	—	`conf`	Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs. VLSI-SoC (Selected Papers) Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner
2003	C	`ed.`	IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003 VLSI-SoC Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf
2003	A	`conf`	Moment-Based Power Estimation in Very Deep Submicron Technologies. ICCAD Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
2003	J	`jnl`	On the Rapid Prototyping of Equalizers for OFDM Systems. Des. Autom. Embed. Syst. Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner
2003	—	`conf`	Reconfiguration requirements for high speed wireless communication systems. FPT Thilo Pionteck, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner
2003	—	`conf`	Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content. MSE Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis, Giuliana Alcántara, Stefan Hoermann, Ralf Steinmetz
2003	C	`conf`	Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models. FDL Leandro Soares Indrusiak, Ricardo Reis, Manfred Glesner
2003	—	`conf`	Switching Activity Estimation in Non-linear Architectures. PATMOS Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2003	C	`conf`	The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. IEEE International Workshop on Rapid System Prototyping Thilo Pionteck, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner
2003	Misc	`conf`	Transition Activity Estimation for General Correlated Data Distributions. VLSI Design Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2003	A	`conf`	Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. DATE Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner
2002	B	`conf`	A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL Thilo Pionteck, Peter Zipf, Lukusa D. Kabulepa, Manfred Glesner
2002	—	`conf`	A discrete algorithm for the regularization of hierarchical VHDL-AMS models. ISCAS (5) Jochen Mades, Diana Estévez Schwarz, Manfred Glesner
2002	—	`conf`	Analysis of bandpass sigma-delta modulator architectures. ICECS Juan Jesús Ocampo Hidalgo, Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	A	`conf`	Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. DATE Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis
2002	—	`conf`	Design of an efficient OFDM burst synchronization scheme. ISCAS (3) Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
2002	A	`conf`	Efficient estimation of signal transition activity in MAC architectures. ISLPED Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	A	`conf`	Estimation of Power Consumption in Encoded Data Buses. DATE Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	B	`ed.`	Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings FPL Manfred Glesner, Peter Zipf, Michel Renovell
2002	B	`conf`	Fly - A Modifiable Hardware Compiler. FPL Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2002	B	`conf`	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. FPL Peter Zipf, Manfred Glesner, Christine Bauer, Hans Wojtkowiak
2002	—	`conf`	Low-power CMOS active resistor independent on the threshold voltage. ICECS Cosmin Popa, Anca Manuela Manolescu, Octavian Mitrea, Manfred Glesner
2002	C	`conf`	On the Rapid Prototyping of Equalizers for OFDM Systems. IEEE International Workshop on Rapid System Prototyping Thilo Pionteck, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella
2002	—	`conf`	Power Consumption in Point-to-Point Interconnect Architectures. SBCCI Alberto García Ortiz, Tudor Murgan, Leandro Soares Indrusiak, Manfred Glesner
2002	C	`conf`	Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. IEEE International Workshop on Rapid System Prototyping Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2002	—	`conf`	Power reduction techniques for an OFDM burst synchronization core. ISCAS (1) Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
2002	C	`conf`	Prototyping of a High Performance Generic Viterbi Decoder. IEEE International Workshop on Rapid System Prototyping Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner
2002	C	`conf`	Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner
2002	A*	`conf`	Regularization of hierarchical VHDL-AMS models using bipartite graphs. DAC Jochen Mades, Manfred Glesner
2002	J	`jnl`	The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications. IEEE Trans. Neural Networks Radu Dogaru, Pedro Julián, Leon O. Chua, Manfred Glesner
2001	J	`jnl`	A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. J. Supercomput. Jürgen Becker, Manfred Glesner
2001	—	`conf`	A low power sinusoidal clock. ISCAS (4) Burkart Voss, Manfred Glesner
2001	—	`conf`	Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2001	—	`conf`	Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner
2001	C	`conf`	Distributed Collaborative Design over Cave2 Framework. VLSI-SOC Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis
2001	B	`conf`	Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner
2001	B	`conf`	Finite-precision analysis of an OFDM burst synchronization scheme. GLOBECOM Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella
2001	—	`conf`	Lower bound on the accuracy of the CORDIC-based frequency offset compensation in burst oriented OFDM systems. VTC Fall Lukusa D. Kabulepa, Tideya Kella, Manfred Glesner
2001	—	`conf`	On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner
2001	C	`conf`	Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner
2001	—	`conf`	Transformierende Synthese zur Verlustleistungsreduktion mittels Partitionierung. MBMV (1) Marc Theisen, Burkart Voss, Manfred Glesner
2000	—	`conf`	A JAVA-Based Mixed-Signal Design Environment. SBCCI Jochen Mades, Thomas Schneider, Manfred Glesner, André Windisch, Wolfgang Ecker
2000	—	`conf`	A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing. EUSIPCO Ahmad Alsolaim, Jürgen Becker, Manfred Glesner, Janusz A. Starzyk
2000	J	`jnl`	A flexible and approximate computing approach for time-frequency distributions. IEEE Trans. Signal Process. Thuyen Le, Manfred Glesner
2000	—	`conf`	Adiabatic charging of long interconnects. ICECS Burkart Voss, Manfred Glesner
2000	—	`conf`	An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000	—	`conf`	An Open VHDL-AMS Simulation Framework. BMAS Thomas Schneider, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker
2000	C	`conf`	An efficient filter bank architecture for the cross-term reduced processing of discrete time-frequency distributions. ISCAS Thuyen Le, Manfred Glesner
2000	Misc	`conf`	Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner
2000	C	`conf`	Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	—	`conf`	Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems. MBMV Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	J	`jnl`	Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. Des. Autom. Embed. Syst. Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	Misc	`conf`	Computing discrete time-frequency distributions using principal component filter bank. ICASSP Thuyen Le, Manfred Glesner
2000	C	`conf`	Configurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations. ISCAS Thuyen Le, Manfred Glesner
2000	B	`conf`	DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL Jürgen Becker, Thilo Pionteck, Manfred Glesner
2000	J	`jnl`	Design methodology of application specific integrated circuits for mechatronic systems. Microprocess. Microsystems Frank-Michael Renner, Karl-Josef Hoffmann, Richard Markert, Manfred Glesner
2000	—	`conf`	Design of random number generators for the HIPERLAN/1 channel access mechanism. ICECS Lukusa D. Kabulepa, Manfred Glesner
2000	A*	`conf`	Direct Bayes Point Machines. ICML Matthias Rychetsky, John Shawe-Taylor, Manfred Glesner
2000	J	`jnl`	Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). Informationstechnik Tech. Inform. André Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker
2000	C	`conf`	Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels. ISCC Ulrich Mayer, Jürgen Deicke, Manfred Glesner
2000	Misc	`conf`	Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk
2000	B	`conf`	Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL Frank-Michael Renner, Jürgen Becker, Manfred Glesner
2000	J	`jnl`	Flexible architectures for DCT of variable-length targeting shape-adaptive transform. IEEE Trans. Circuits Syst. Video Technol. Thuyen Le, Manfred Glesner
2000	C	`conf`	Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams. IEEE International Workshop on Rapid System Prototyping Ulrich Mayer, Manfred Glesner
2000	Misc	`conf`	IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA Jürgen Becker, Manfred Glesner
2000	C	`conf`	Rotating stall analysis using signal-adapted filter bank and Cohen's time-frequency distributions. ISCAS Thuyen Le, Manfred Glesner
2000	C	`conf`	Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner
2000	C	`conf`	Statistical modelling of the MPEG-4 FlexMux. ISCAS Ulrich Mayer, Jürgen Deicke, Manfred Glesner
2000	J	`jnl`	Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints). Informationstechnik Tech. Inform. Frank-Michael Renner, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
1999	Misc	`conf`	A data-driven scheme for the approximated computing of alias-free generalized discrete time-frequency distributions. ICASSP Thuyen Le, Manfred Glesner
1999	—	`conf`	A flexible subband-based computation scheme for generalized discrete time-frequency distributions. ICECS Thuyen Le, Manfred Glesner
1999	Misc	`conf`	A new flexible architecture for variable length DCT targeting shape-adaptive transform. ICASSP Thuyen Le, Manfred Glesner
1999	B	`conf`	Accelerated training of support vector machines. IJCNN Matthias Rychetsky, Stefan Ortmann, Michael Ullmann, Manfred Glesner
1999	J	`jnl`	Bus-based communication synthesis on system level. ACM Trans. Design Autom. Electr. Syst. Michael Gasteier, Manfred Glesner
1999	C	`conf`	Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping Frank-Michael Renner, Jürgen Becker, Manfred Glesner
1999	Misc	`conf`	Design and Test of MEMs. VLSI Design Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
1999	B	`conf`	Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker
1999	J	`jnl`	Fuzzy segmented image coding using orthonormal bases and derivative chain coding. Pattern Recognit. Alexander Steudel, Manfred Glesner
1999	—	`conf`	ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1999	—	`conf`	MPEG-4 PC - Authoring and Playing of MPEG-4 Content for Local and Broadcast Applications. ECMAST Peter Gerken, Stefan Schultz, Gerald Knabe, Franco Casalino, Gianluca Di Cagno, Mauro Quaglia, Jean-Claude Dufourd, Souhila Boughoufalah, Frédéric Bouilhaguet, Michael Stepping, Thomas Bonse, Ulrich Mayer, Jürgen Deicke, Manfred Glesner
1999	J	`jnl`	Mikrosystemtechnik. Informationstechnik Tech. Inform. Manfred Glesner
1999	—	`conf`	Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner
1999	B	`conf`	On the variance reduction of neural networks-experimental results for an automotive application. IJCNN Stefan Ortmann, Matthias Rychetsky, Manfred Glesner
1999	—	`conf`	Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu
1999	B	`conf`	Perceptrons revisited: the addition of a non-monotone recursion greatly enhances their representation and classification properties. IJCNN Radu Dogaru, Marinel Alangiu, Matthias Rychetsky, Manfred Glesner
1999	B	`conf`	Support vector approaches for engine knock detection. IJCNN Matthias Rychetsky, Stefan Ortmann, Manfred Glesner
1998	—	`conf`	A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1998	J	`jnl`	A client/server application as an example for MPEG-4 systems. Comput. Commun. Jürgen Deicke, Ulrich Mayer, Manfred Glesner
1998	—	`conf`	Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem. EUROMICRO Manfred Glesner, Matthias Rychetsky, Stefan Ortmann
1998	B	`conf`	An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL Frank-Michael Renner, Jürgen Becker, Manfred Glesner
1998	—	`conf`	Constructive Learning of a Sub-Feature Detector Network by Means of Prediction Risk Estimation. NC Stefan Ortmann, Matthias Rychetsky, Manfred Glesner
1998	J	`jnl`	Development and Implementation of a Neural Knock Detector Using Constructive Learning Methods. Int. J. Uncertain. Fuzziness Knowl. Based Syst. Stefan Ortmann, Manfred Glesner
1998	—	`conf`	Flexible Multiplexing in MPEG-4 Systems. IDMS Jürgen Deicke, Ulrich Mayer, Angelika Knoll, Manfred Glesner
1998	A	`conf`	Generation of Interconnect Topologies for Communication Synthesis. DATE Michael Gasteier, Manfred Glesner, Michael Münch
1998	—	`conf`	HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner
1998	—	`conf`	Internet-based Training of Reconfigurable Technologies. SBCCI Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
1998	B	`conf`	Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner
1998	—	`conf`	Pruning and Regularization Techniques for Feed Forward Nets Applied on a Real World Data Base. NC Matthias Rychetsky, Stefan Ortmann, Manfred Glesner
1998	J	`jnl`	Rapid Prototyping of Real-Time Information Processing Units for Mechatronic Systems. Real Time Syst. Hans-Jürgen Herpel, Manfred Glesner
1998	C	`conf`	Rapid Prototyping of a Co-Processor Based Engine Knock Detection System. International Workshop on Rapid System Prototyping Andreas Kirschbaum, Stefan Ortmann, Manfred Glesner
1998	C	`conf`	Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping Andreas Kirschbaum, Jürgen Becker, Manfred Glesner
1998	—	`conf`	Sound signature analysis using time-frequency signal processing: Application to active stall avoidance in axial compressors. EUSIPCO Thuyen Le, Thomas Dombek, Manfred Glesner
1998	—	`conf`	State-of-the-Art in Rapid Prototyping. SBCCI Manfred Glesner, Andreas Kirschbaum
1997	B	`conf`	A prototyping environment for fuzzy controllers. FPL Thomas Hollstein, Andreas Kirschbaum, Manfred Glesner
1997	J	`jnl`	Advanced data preprocessing using fuzzy clustering techniques. Fuzzy Sets Syst. Harald Genther, Manfred Glesner
1997	—	`conf`	An Object-Oriented Client/Server Architecture for Video-on-Demand Applications. IDMS Jürgen Deicke, Ulrich Mayer, Manfred Glesner
1997	J	`jnl`	An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions. ACM Trans. Design Autom. Electr. Syst. Michael Münch, Norbert Wehn, Manfred Glesner
1997	—	`conf`	Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. ED&TC M. Lang, D. David, Manfred Glesner
1997	A*	`conf`	CAD and Foundries for Microsystems. DAC Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, Paul Drake, András Poppe, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner
1997	J	`jnl`	Determination of target volumes for three-dimensional radiotherapy of cancer patients with a fuzzy system. Fuzzy Sets Syst. T. Waschek, S. Levegrün, M. van Kampen, Manfred Glesner, R. Engenhart-Cabillic, Wolfgang Schlegel
1997	B	`ed.`	Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings FPL Wayne Luk, Peter Y. K. Cheung, Manfred Glesner
1997	—	`conf`	Generation of the HDL-A-model of a micromembrane from its finite-element-description. ED&TC Klaus Hofmann, Manfred Glesner, Nicu Sebe, Anca Manuela Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois
1997	C	`conf`	Hardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems. IEEE International Workshop on Rapid System Prototyping Thuyen Le, Frank-Michael Renner, Manfred Glesner
1997	C	`conf`	Rapid prototyping of communication architectures. IEEE International Workshop on Rapid System Prototyping Andreas Kirschbaum, Manfred Glesner
1996	—	`conf`	An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. ISSS Michael Münch, Manfred Glesner, Norbert Wehn
1996	—	`conf`	Applied design and analysis of microsystems. ED&TC Jean-Michel Karam, Bernard Courtois, András Poppe, Klaus Hofmann, Márta Rencz, Manfred Glesner, Vladimír Székely
1996	—	`conf`	Bus-Based Communication Synthesis on System-Level. ISSS Michael Gasteier, Manfred Glesner
1996	B	`conf`	CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping. FPL Ulrike Ober, Hans-Jürgen Herpel, Manfred Glesner
1996	J	`jnl`	Computer-aided design of fuzzy systems based on generic VHDL specifications. IEEE Trans. Fuzzy Syst. Thomas Hollstein, Saman K. Halgamuge, Manfred Glesner
1996	B	`ed.`	Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings FPL Reiner W. Hartenstein, Manfred Glesner
1996	—	`conf`	Image coding with fuzzy region-growing segmentation. ICIP (2) Alexander Steudel, Manfred Glesner
1996	C	`conf`	Rapid-Prototyping of a CAN-Bus Controller: A Case Study. RSP Andreas Kirschbaum, Frank-Michael Renner, Alexander Wilmes, Manfred Glesner
1996	—	`conf`	Searching for robust chaos in discrete time neural networks using weight space exploration. ICNN Radu Dogaru, A. T. Murgan, Stefan Ortmann, Manfred Glesner
1995	Misc	`conf`	A sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems. SAC Saman K. Halgamuge, Christoph Grimm, Manfred Glesner
1995	B	`conf`	Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. FPL U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
1995	J	`jnl`	An alternative approach for generation of membership functions and fuzzy rules based on radial and cubic basis function networks. Int. J. Approx. Reason. Saman K. Halgamuge, Werner Pöchmüller, Manfred Glesner
1995	Misc	`conf`	Comparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers. SAC Saman K. Halgamuge, Alain Brichard, Manfred Glesner
1995	J	`jnl`	Fuzzy neural networks: between functional equivalence and applicability. Int. J. Neural Syst. Saman K. Halgamuge, Manfred Glesner
1995	Misc	`conf`	Multidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets. SAC Thomas A. Runkler, Manfred Glesner
1995	—	`conf`	Multiway netlist partitioning onto FPGA-based board architecture. EURO-DAC Ulrike Ober, Manfred Glesner
1995	B	`conf`	Prototype Generation of Application-Specific Embedded Controllers for Microsystems. FPL Hans-Jürgen Herpel, Ulrike Ober, Manfred Glesner
1995	C	`conf`	Rapid prototyping in microsystems development. RSP Hans-Jürgen Herpel, Manfred Glesner, Horst Eggert, Wolfgang Süß, Martina Gorges-Schleuter, Wilfried Jakob
1995	J	`jnl`	Visual inspection in industrial manufacturing. IEEE Micro Andreas König, Peter Windirsch, Michael Gasteier, Manfred Glesner
1994	—	`conf`	A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems. HICSS (1) Hans-Jürgen Herpel, Michael Held, Manfred Glesner
1994	Misc	`conf`	Automatic generation of a fuzzy classification system using fuzzy clustering methods. SAC Harald Genther, Manfred Glesner
1994	Misc	`conf`	DECADE - fast centroid approximation defuzzification for real time fuzzy control applications. SAC Thomas A. Runkler, Manfred Glesner
1994	Misc	`conf`	Fuzzy neural fusion techniques for industrial applications. SAC Saman K. Halgamuge, Manfred Glesner
1994	—	`conf`	Generating compilers for generated datapaths. EURO-DAC Michael Held, Manfred Glesner
1994	B	`conf`	MCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems. MASCOTS Hans-Jürgen Herpel, Michael Held, Manfred Glesner
1994	—	`conf`	Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC Wolfgang Ecker, Manfred Glesner, Andreas Vombach
1994	—	`conf`	Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays. Fuzzy Days Thomas Hollstein, Saman K. Halgamuge, Andreas Kirschbaum, Manfred Glesner
1994	A	`conf`	Systematic Methods for Multivariate Data Visualization and Numerical Assessment of Class Separability and Overlap in Automated Visual Industrial Quality Control. BMVC Andreas König, Olaf Bulmahn, Manfred Glesner
1993	—	`conf`	A rule based prototype system for automatic classification in industrial quality control. ICNN Saman K. Halgamuge, Werner Pöchmüller, Manfred Glesner
1993	—	`conf`	Approximative Synthese von Fuzzy - Controllern. Fuzzy Days Thomas A. Runkler, Manfred Glesner
1993	—	`conf`	Echtzeit Fahrbahnzustandserkennung mit Fuzzy-Neuronalen Netzen. Fuzzy Days Saman K. Halgamuge, Hans-Jürgen Herpel, Manfred Glesner
1993	—	`conf`	Estimating lower hardware bounds in high-level synthesis. VLSI Norbert Wehn, Manfred Glesner, C. Vielhauer
1993	—	`conf`	High-level synthesis transformations for programmable architectures. EURO-DAC Peter Poechmueller, Manfred Glesner, Fang Longsen
1993	—	`conf`	Is LVQ really good for classification?-an interesting alternative. ICNN Werner Pöchmüller, Manfred Glesner, H. Juergs
1993	—	`conf`	Neural and associative modules in a hybrid dynamic system for visual industrial quality control. ICNN Andreas König, Harald Genther, Manfred Glesner
1993	—	`conf`	Real-Time System Prototyping Based on a Heterogeneous Multi-Processor Environment. RTS Hans-Jürgen Herpel, Michael Held, Manfred Glesner
1993	—	`conf`	Synthesis of complex VHDL operators. EURO-DAC Michael Gasteier, Norbert Wehn, Manfred Glesner
1992	—	`conf`	Application-specific microelectronics for mechatronic systems. EURO-DAC Peter Windirsch, Hans-Jürgen Herpel, Andreas Laudenbach, Manfred Glesner
1992	—	`conf`	Associative information processing: algorithms and system. ASAP Werner Pöchmüller, Andreas König, Manfred Glesner
1992	B	`conf`	High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. FPL Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen
1992	—	`conf`	High-level synthesis in a rapid-prototype environment for mechatronic systems. EURO-DAC Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner
1992	J	`jnl`	VLSI system design for automotive control. IEEE J. Solid State Circuits Andreas Laudenbach, Manfred Glesner
1991	—	`conf`	A CAD tool for designing large, fault-tolerant VLSI arrays. Great Lakes Symposium on VLSI Peter Poechmueller, G. K. Sharma, Manfred Glesner
1991	—	`conf`	A New Approach for Designing Fault-Tolerant Array Processors. Fault-Tolerant Computing Systems Peter Poechmueller, Manfred Glesner
1991	—	`conf`	A VLSI System Design for the Control of High Performance Combustion Engines. VLSI Andreas Laudenbach, Manfred Glesner, Norbert Wehn
1991	—	`conf`	A VLSI implementation of a state variable filter algorithm. Great Lakes Symposium on VLSI Hans-Jürgen Herpel, Peter Windirsch, Manfred Glesner, J. Führer, J. Busshardt
1991	—	`conf`	A new approach to timing driven partitioning of combinational logic. Great Lakes Symposium on VLSI Norbert Wehn, Manfred Glesner
1991	—	`conf`	An approach for multilevel logic cell optimization in module generators. Great Lakes Symposium on VLSI Peter Poechmueller, Manfred Glesner
1991	—	`conf`	HADES-high-level architecture development and exploration system. Great Lakes Symposium on VLSI Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner
1991	C	`conf`	RAMSES-a rapid prototyping environment for embedded control applications. RSP Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
1991	—	`conf`	Verifikation mikroelektronischer Systeme zur Prozeßsteuerung durch schnelle Prototypenrealisierung. ASIM Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner
1990	J	`jnl`	Evaluation of state-of-the-art neural network customized hardware. Neurocomputing Werner Pöchmüller, Manfred Glesner
1990	B	`conf`	Handwritten pattern recognition with a binary associative memory. IJCNN Werner Pöchmüller, Manfred Glesner
1990	—	`conf`	Timing Driven Partitioning of Combinational Logic. Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme Norbert Wehn, Manfred Glesner, A. Kister, S. Kastner
1988	A*	`conf`	A Defect-Tolerant and Fully Testable PLA. DAC Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth
1988	—	`conf`	Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. GI Jahrestagung (2) Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe
1987	A*	`conf`	The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. DAC Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp
1986	A*	`conf`	SCAT - a new statistical timing verifier in a silicon compiler system. DAC Manfred Glesner, Johannes Schuck, R. B. Steck
1986	J	`jnl`	Statische und dynamische CMOS-Schaltungstechniken im Vergleich. it Inf. Technol. Norbert Wehn, Manfred Glesner