Manash Chanda

12 papers Journal 10Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
Breast-Cancer Cell Lines Recognition: Modeling and Simulation With Repulsive Steric Hindrance Approach.
IEEE Trans. Consumer Electron.
Amit Bhattacharyya, Srinivasa Rao Karumuri, Manash Chanda
2024 — conf
Ventricular Dysfunction and Organ Transplant Rejection Determinant Biomarker Recognition in Serum via Charge Deduction Method.
ICCCNT
Amit Bhattacharyya, Proma Nag, Santanu Maity, Pinaki Satpathy, Papiya Debnath, Manash Chanda
2023 J jnl
A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications.
Microelectron. J.
Adrija Mukherjee, Papiya Debnath, D. Nirmal, Manash Chanda
2022 J jnl
Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime.
Comput. Electr. Eng.
Tanushree Ganguli, Manash Chanda, Angsuman Sarkar
2022 J jnl
Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor.
Comput. Electr. Eng.
Gargi Jana, Dipanjan Sen, Papiya Debnath, Manash Chanda
2021 J jnl
Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm.
IEEE Trans. Artif. Intell.
Shreya Bhattacharyya, Souvik Majumder, Papiya Debnath, Manash Chanda
2020 J jnl
Split gated silicon nanotube FET for bio-sensing applications.
IET Circuits Devices Syst.
Avtar Singh, Saurabh Chaudhury, Manash Chanda, Chandan Kumar Sarkar
2018 J jnl
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing.
IET Circuits Devices Syst.
Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar
2017 J jnl
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application.
J. Low Power Electron.
Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar
2015 J jnl
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application.
J. Circuits Syst. Comput.
Manash Chanda, Swapnadip De, Chandan Kumar Sarkar
2015 J jnl
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application.
IEEE Trans. Very Large Scale Integr. Syst.
Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar
2014 — conf
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application.
VDAT
Manash Chanda, Ananda Sankar Chakraborty, S. Nag, Raina Modak