Mamidala Jagadesh Kumar

13 papers Misc 7Journal 6
YearRankTypeTitle / Venue / Authors
2025 Misc conf
Physical Insights into the Leakage Mechanisms Governing the Scaling Trends in 4H-SiC Based Junctionless FETs.
VLSID
Jaspreet Singh, Aakash Kumar Jain, Mamidala Jagadesh Kumar
2020 J jnl
Sub-10 nm Scalability of Junctionless FETs Using a Ground Plane in High-K BOX: A Simulation Study.
IEEE Access
Aakash Kumar Jain, Mamidala Jagadesh Kumar
2017 J jnl
Comprehensive Analysis of Gate-Induced Drain Leakage in Emerging FET Architectures: Nanotube FETs Versus Nanowire FETs.
IEEE Access
Shubham Sahay, Mamidala Jagadesh Kumar
2017 Misc conf
DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions.
VLSID
Rajat Vishnoi, Pratyush Panday, Mamidala Jagadesh Kumar
2017 J jnl
Double gate symmetric tunnel FET: investigation and analysis.
IET Circuits Devices Syst.
Sindhu Ramaswamy, Mamidala Jagadesh Kumar
2012 Misc conf
Modeling of Partially Depleted SOI DEMOSFETs with a Sub-circuit Utilizing the HiSIM-HV Compact Model.
VLSI Design
Tarun Kumar Agarwal, Mamidala Jagadesh Kumar
2010 Misc conf
A New Hetero-material Stepped Gate (HSG) SOI LDMOS for RF Power Amplifier Applications.
VLSI Design
Radhakrishnan Sithanandam, Mamidala Jagadesh Kumar
2007 Misc conf
Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Analog Circuit Simulation.
VLSI Design
Mamidala Jagadesh Kumar, Vivek Venkataraman, Susheel Nawal
2004 Misc conf
A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors.
VLSI Design
Mamidala Jagadesh Kumar, Vinod Parihar
2004 J jnl
Investigation of the novel attributes of a single-halo double gate SOI MOSFET: 2D simulation study.
Microelectron. J.
G. Venkateshwar Reddy, Mamidala Jagadesh Kumar
2003 J jnl
2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI.
Microelectron. Reliab.
Mamidala Jagadesh Kumar, Linga Reddy Cenkeramaddi
2003 Misc conf
A New Lateral SiGe-Base PNM Schottky Collector Bipolar Transistor on SOI for Non-saturating VLSI Logic Design.
VLSI Design
Mamidala Jagadesh Kumar, D. Venkateshrao
2002 J jnl
Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFET.
IEEE Trans. Reliab.
Mamidala Jagadesh Kumar, Vikram Verma