Malgorzata Marek-Sadowska

244 papers A* 40A 43C 19Misc 2Journal 71Unranked 67

Year	Rank	Type	Title / Venue / Authors
2023	—	`conf`	ISPD 2023 Lifetime Achievement Award Bio. ISPD Malgorzata Marek-Sadowska
2019	—	`conf`	Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration. ACM Great Lakes Symposium on VLSI Ali Abbasinasab, Malgorzata Marek-Sadowska
2018	J	`jnl`	High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators. IEEE Trans. Very Large Scale Integr. Syst. Ping-Lin Yang, Malgorzata Marek-Sadowska
2018	A*	`conf`	RAIN: a tool for reliability assessment of interconnect networks - physics to software. DAC Ali Abbasinasab, Malgorzata Marek-Sadowska
2016	C	`conf`	A fast, fully verifiable, and hardware predictable ASIC design methodology. ICCD Ping-Lin Yang, Malgorzata Marek-Sadowska
2016	—	`conf`	AFD-based method for signal line EM reliability evaluation. ISQED Zhong Guan, Malgorzata Marek-Sadowska
2016	A	`conf`	An efficient and accurate algorithm for computing RC current response with applications to EM reliability evaluation. ICCAD Zhong Guan, Malgorzata Marek-Sadowska
2016	J	`jnl`	Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence. IEEE Trans. Very Large Scale Integr. Syst. Zhong Guan, Malgorzata Marek-Sadowska
2016	A	`conf`	Making split-fabrication more secure. ICCAD Ping-Lin Yang, Malgorzata Marek-Sadowska
2015	J	`jnl`	A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures. IEEE Trans. Very Large Scale Integr. Syst. Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
2015	—	`conf`	Blech Effect in Interconnects: Applications and Design Guidelines. ISPD Ali Abbasinasab, Malgorzata Marek-Sadowska
2015	—	`conf`	Machine Learning in Simulation-Based Analysis. ISPD Li-C. Wang, Malgorzata Marek-Sadowska
2015	J	`jnl`	T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool. IEEE Trans. Very Large Scale Integr. Syst. Di-An Li, Malgorzata Marek-Sadowska, Sani R. Nassif
2015	J	`jnl`	Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips. IEEE Trans. Very Large Scale Integr. Syst. Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly
2014	J	`jnl`	Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech P. Maly
2014	—	`conf`	Estimating true worst currents for power grid electromigration analysis. ISQED Di-An Li, Malgorzata Marek-Sadowska
2014	J	`jnl`	On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study. IEEE Comput. Archit. Lett. Vivek S. Nandakumar, Malgorzata Marek-Sadowska
2014	—	`conf`	Statistical analysis of process variation induced SRAM electromigration degradation. ISQED Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
2014	A*	`conf`	System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs. DAC Vivek S. Nandakumar, Malgorzata Marek-Sadowska
2013	—	`conf`	Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure. ISPD Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
2013	J	`jnl`	Routing Challenges for Designs With Super High Pin Density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiang Qiu, Malgorzata Marek-Sadowska
2013	—	`conf`	SRAM bit-line electromigration mechanism and its prevention scheme. ISQED Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif
2012	J	`jnl`	A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures. IEEE J. Emerg. Sel. Topics Circuits Syst. Vivek S. Nandakumar, Malgorzata Marek-Sadowska
2012	A*	`conf`	Can pin access limit the footprint scaling? DAC Xiang Qiu, Malgorzata Marek-Sadowska
2012	—	`conf`	Post-placement lithographic hotspot detection and removal in one-dimensional gridded designs. ISQED Jen-Yi Wuu, Mark Simmons, Malgorzata Marek-Sadowska
2012	—	`conf`	Vertical Slit Field Effect Transistor in ultra-low power applications. ISQED Xiang Qiu, Malgorzata Marek-Sadowska, Wojciech Maly
2011	A*	`conf`	Layout effects in fine grain 3D integrated regular microprocessor blocks. DAC Vivek S. Nandakumar, Malgorzata Marek-Sadowska
2011	C	`conf`	Low power, high throughput network-on-chip fabric for 3D multicore processors. ICCD Vivek S. Nandakumar, Malgorzata Marek-Sadowska
2011	—	`conf`	Metrics for characterizing machine learning-based hotspot detection methods. ISQED Jen-Yi Wuu, Fedor G. Pikus, Malgorzata Marek-Sadowska
2011	J	`jnl`	On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2011	—	`conf`	On old and new routing problems. ISPD Malgorzata Marek-Sadowska
2011	J	`jnl`	Performance Optimization Using Variable-Latency Design Style. IEEE Trans. Very Large Scale Integr. Syst. Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2011	J	`jnl`	Power Delivery for Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Malgorzata Marek-Sadowska
2011	—	`conf`	Rapid layout pattern classification. ASP-DAC Jen-Yi Wuu, Fedor G. Pikus, Andres J. Torres, Malgorzata Marek-Sadowska
2011	J	`jnl`	Reliability Analysis and Optimization of Power-Gated ICs. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Malgorzata Marek-Sadowska
2011	A	`conf`	Variation-aware electromigration analysis of power/ground networks. ICCAD Di-An Li, Malgorzata Marek-Sadowska
2010	J	`jnl`	Layout Generator for Transistor-Level High-Density Regular Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2010	—	`conf`	On-chip em-sensitive interconnect structures. SLIP Di-An Li, Malgorzata Marek-Sadowska, Bill Lee
2010	—	`conf`	Performance study of VeSFET-based, high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2010	—	`conf`	Statistical static timing analysis flow for transistor level macros in a microprocessor. ISQED Vivek S. Nandakumar, David Newmark, Yaping Zhan, Malgorzata Marek-Sadowska
2009	—	`conf`	A study of decoupling capacitor effectiveness in power and ground grid networks. ISQED Aida Todri, Malgorzata Marek-Sadowska, Francois Maire, Christophe Matheron
2009	A	`conf`	Electromigration study of power-gated grids. ISLPED Aida Todri, Malgorzata Marek-Sadowska
2009	J	`jnl`	Spare Cells With Constant Insertion for Engineering Change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2009	J	`jnl`	Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2009	—	`conf`	Transistor-level layout of high-density regular circuits. ISPD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly
2008	C	`conf`	A study of reliability issues in clock distribution networks. ICCD Aida Todri, Malgorzata Marek-Sadowska
2008	C	`conf`	ECO-Map: Technology remapping for post-mask ECO using simulated annealing. ICCD Nilesh Modi, Malgorzata Marek-Sadowska
2008	J	`jnl`	Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2008	C	`conf`	Is there always performance overhead for regular fabric? ICCD Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly, Andrzej Pfitzner, Dominik Kasprowicz
2008	A*	`conf`	Power gating scheduling for power/ground noise reduction. DAC Hailin Jiang, Malgorzata Marek-Sadowska
2008	A	`conf`	Power supply noise aware workload assignment for multi-core systems. ICCAD Aida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya
2008	C	`conf`	Timing analysis considering IR drop waveforms in power gating designs. ICCD Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2008	—	`conf`	Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2007	A*	`conf`	An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. DAC Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A	`conf`	Analysis and optimization of power-gated ICs with multiple power gating configurations. ICCAD Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang
2007	A	`conf`	Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A	`conf`	Engineering change using spare cells with constant insertion. ICCAD Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
2007	A*	`conf`	OPC-Free and Minimally Irregular IC Design Style. DAC Wojciech Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
2007	—	`conf`	Power-Gating Aware Floorplanning. ISQED Hailin Jiang, Malgorzata Marek-Sadowska
2007	J	`jnl`	Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chao-Yang Yeh, Malgorzata Marek-Sadowska
2007	—	`ch.`	mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement. Modern Circuit Placement Bo Hu, Malgorzata Marek-Sadowska
2006	J	`jnl`	Analysis and methodology for multiple-fault diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	—	`conf`	Analysis of Process Variation's Effect on SRAM's Read Stability. ISQED Chung-Kuan Tsai, Malgorzata Marek-Sadowska
2006	—	`conf`	Delay Fault Diagnosis for Non-Robust Test. ISQED Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
2006	J	`jnl`	Designing via-configurable logic blocks for regular fabric. IEEE Trans. Very Large Scale Integr. Syst. Yajun Ran, Malgorzata Marek-Sadowska
2006	C	`conf`	Power/ground supply network optimization for power-gating. ICCD Hailin Jiang, Malgorzata Marek-Sadowska
2006	J	`jnl`	Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qinghua Liu, Malgorzata Marek-Sadowska
2006	A	`conf`	Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2006	J	`jnl`	Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. IEEE Trans. Very Large Scale Integr. Syst. Yajun Ran, Malgorzata Marek-Sadowska
2005	—	`conf`	A congestion-driven placement framework with local congestion prediction. ACM Great Lakes Symposium on VLSI Qinghua Liu, Malgorzata Marek-Sadowska
2005	J	`jnl`	A study of netlist structure and placement efficiency. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Qinghua Liu, Malgorzata Marek-Sadowska
2005	—	`conf`	An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. ISQED Chung-Kuan Tsai, Malgorzata Marek-Sadowska
2005	C	`conf`	Benefits and Costs of Power-Gating Technique. ICCD Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
2005	—	`conf`	Clock skew bounds estimation under power supply and process variations. ACM Great Lakes Symposium on VLSI Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska
2005	J	`jnl`	Delay-fault diagnosis using timing information. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2005	J	`jnl`	Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
2005	J	`jnl`	General skew constrained clock network sizing based on sequential linear programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
2005	J	`jnl`	Multilevel fixed-point-addition-based VLSI placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Hu, Malgorzata Marek-Sadowska
2005	J	`jnl`	On-chip power-supply network optimization using multigrid-based technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kai Wang, Malgorzata Marek-Sadowska
2005	C	`conf`	Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. ICCD Qinghua Liu, Malgorzata Marek-Sadowska
2005	A	`conf`	Skew-programmable clock design for FPGA and skew-aware placement. FPGA Chao-Yang Yeh, Malgorzata Marek-Sadowska
2005	A	`conf`	Timing-aware power noise reduction in layout. ICCAD Chao-Yang Yeh, Malgorzata Marek-Sadowska
2005	A	`conf`	Via-configurable routing architectures and fast design mappability estimation for regular fabrics. ICCAD Yajun Ran, Malgorzata Marek-Sadowska
2005	—	`conf`	Wire length prediction-based technology mapping and fanout optimization. ISPD Qinghua Liu, Malgorzata Marek-Sadowska
2005	—	`conf`	mFAR: fixed-points-addition-based VLSI placement algorithm. ISPD Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska
2004	—	`conf`	A study of netlist structure and placement efficiency. ISPD Qinghua Liu, Malgorzata Marek-Sadowska
2004	A	`conf`	An integrated design flow for a via-configurable gate array. ICCAD Yajun Ran, Malgorzata Marek-Sadowska
2004	A*	`conf`	Buffer sizing for clock power minimization subject to general skew constraints. DAC Kai Wang, Malgorzata Marek-Sadowska
2004	—	`conf`	Clock network sizing via sequential linear programming with time-domain analysis. ISPD Kai Wang, Malgorzata Marek-Sadowska
2004	—	`conf`	Delay Fault Diagnosis Using Timing Information. ISQED Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	—	`conf`	Designing a via-configurable regular fabric. CICC Yajun Ran, Malgorzata Marek-Sadowska
2004	C	`conf`	Diagnosis of Hold Time Defects. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2004	A	`conf`	Eliminating False Positives in Crosstalk Noise Analysis. DATE Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
2004	J	`jnl`	Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
2004	J	`jnl`	Fine granularity clustering-based placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bo Hu, Malgorzata Marek-Sadowska
2004	J	`jnl`	Individual wire-length prediction with application to timing-driven placement. IEEE Trans. Very Large Scale Integr. Syst. Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
2004	A	`conf`	Multilevel expansion-based VLSI placement with blockages. ICCAD Bo Hu, Malgorzata Marek-Sadowska
2004	A*	`conf`	On designing via-configurable cell blocks for regular fabrics. DAC Yajun Ran, Malgorzata Marek-Sadowska
2004	J	`jnl`	Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
2004	C	`conf`	Potential Slack Budgeting with Clock Skew Optimization. ICCD Kai Wang, Malgorzata Marek-Sadowska
2004	A*	`conf`	Pre-layout wire length and congestion estimation. DAC Qinghua Liu, Malgorzata Marek-Sadowska
2004	J	`jnl`	Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. Chao-Yang Yeh, Malgorzata Marek-Sadowska
2004	C	`conf`	The Magic of a Via-Configurable Regular Fabric. ICCD Yajun Ran, Malgorzata Marek-Sadowska
2003	—	`conf`	A crosstalk aware two-pin net router. ISCAS (5) Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
2003	J	`jnl`	A new reasoning scheme for efficient redundancy addition and removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska
2003	A	`conf`	An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
2003	J	`jnl`	Buffer delay change in the presence of power and ground noise. IEEE Trans. Very Large Scale Integr. Syst. Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
2003	J	`jnl`	Clock and Power Gating with Timing Closure. IEEE Des. Test Comput. Arindam Mukherjee, Malgorzata Marek-Sadowska
2003	A*	`conf`	Crosstalk noise in FPGAs. DAC Yajun Ran, Malgorzata Marek-Sadowska
2003	A*	`conf`	Delay budgeting in sequential circuit with application on FPGA placement. DAC Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	—	`conf`	Fine granularity clustering for large scale placement problems. ISPD Bo Hu, Malgorzata Marek-Sadowska
2003	A*	`conf`	Gain-based technology mapping for discrete-size cell libraries. DAC Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
2003	—	`conf`	Minimizing Inter-Clock Coupling Jitter. ISQED Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
2003	—	`conf`	Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
2003	A	`conf`	Minimum-Area Sequential Budgeting for FPGA. ICCAD Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	—	`conf`	Modeling Crosstalk Induced Delay. ISQED Chung-Kuan Tsai, Malgorzata Marek-Sadowska
2003	C	`conf`	Multiple Fault Diagnosis Using n-Detection Tests. ICCD Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
2003	A*	`conf`	On-chip power supply network optimization using multigrid-based technique. DAC Kai Wang, Malgorzata Marek-Sadowska
2003	J	`jnl`	PITIA: an FPGA for throughput-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
2003	A	`conf`	Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. DATE Kai Wang, Malgorzata Marek-Sadowska
2003	—	`conf`	Sequential delay budgeting with interconnect prediction. SLIP Chao-Yang Yeh, Malgorzata Marek-Sadowska
2003	—	`conf`	Synthesis and placement flow for gain-based programmable regular fabrics. ISPD Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska
2003	A*	`conf`	Temporofunctional crosstalk noise analysis. DAC Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
2003	J	`jnl`	Wave steering to integrate logic and physical syntheses. IEEE Trans. Very Large Scale Integr. Syst. Arindam Mukherjee, Malgorzata Marek-Sadowska
2003	A*	`conf`	Wire length prediction based clustering and its application in placement. DAC Bo Hu, Malgorzata Marek-Sadowska
2003	—	`conf`	Wire length prediction in constraint driven placement. SLIP Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
2002	A	`conf`	ATPG-based logic synthesis: an overview. ICCAD Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
2002	A	`conf`	Closed-Form Crosstalk Noise Metrics for Physical Design Applications. DATE Lauren Hui Chen, Malgorzata Marek-Sadowska
2002	A	`conf`	Congestion minimization during placement without estimation. ICCAD Bo Hu, Malgorzata Marek-Sadowska
2002	A*	`conf`	Coping with buffer delay change due to power and ground noise. DAC Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
2002	—	`conf`	Efficient Closed-Form Crosstalk Delay Metrics. ISQED Lauren Hui Chen, Malgorzata Marek-Sadowska
2002	A	`conf`	Efficient circuit clustering for area and power reduction in FPGAs. FPGA Amit Singh, Malgorzata Marek-Sadowska
2002	J	`jnl`	Efficient circuit clustering for area and power reduction in FPGAs. ACM Trans. Design Autom. Electr. Syst. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
2002	—	`conf`	FAR: fixed-points addition & relaxation based placement. ISPD Bo Hu, Malgorzata Marek-Sadowska
2002	—	`conf`	FPGA interconnect planning. SLIP Amit Singh, Malgorzata Marek-Sadowska
2002	—	`conf`	Incremental delay change due to crosstalk noise. ISPD Lauren Hui Chen, Malgorzata Marek-Sadowska
2002	A	`conf`	Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. DATE Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska
2002	J	`jnl`	Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis. VLSI Design Tong Xiao, Malgorzata Marek-Sadowska
2001	C	`conf`	A Global Routing Technique for Wave-Steering Design Methodology. DSD Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
2001	J	`jnl`	Aggressor alignment for worst-case crosstalk noise. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lauren Hui Chen, Malgorzata Marek-Sadowska
2001	A*	`conf`	Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. DAC Tong Xiao, Malgorzata Marek-Sadowska
2001	C	`conf`	Gate Sizing to Eliminate Crosstalk Induced Timing Violation. ICCD Tong Xiao, Malgorzata Marek-Sadowska
2001	A	`conf`	In-place delay constrained power optimization using functional symmetries. DATE Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska
2001	A	`conf`	Interconnect Resource-Aware Placement for Hierarchical FPGAs. ICCAD Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
2001	—	`conf`	Interconnect complexity-aware FPGA placement using Rent's rule. SLIP Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
2001	A	`conf`	Interconnect pipelining in a throughput-intensive FPGA architecture. FPGA Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
2001	A*	`conf`	Latency and Latch Count Minimization in Wave Steered Circuits. DAC Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
2001	A*	`conf`	Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. DAC Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska
2001	A	`conf`	Single-Pass Redundancy Addition and Removal. ICCAD Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
2001	—	`conf`	Who are the alternative wires in your neighborhood? (alternative wires identification without search). ACM Great Lakes Symposium on VLSI Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
2000	A	`conf`	A novel high throughput reconfigurable FPGA architecture. FPGA Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
2000	—	`conf`	Aggressor alignment for worst-case coupling noise. ISPD Lauren Hui Chen, Malgorzata Marek-Sadowska
2000	—	`conf`	Efficient Delay Calculation in Presence of Crosstalk. ISQED Tong Xiao, Malgorzata Marek-Sadowska
2000	A*	`conf`	Fast post-placement rewiring using easily detectable functional symmetries. DAC Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
2000	J	`jnl`	OBDD Minimization Based on Two-Level Representation of Boolean Functions. IEEE Trans. Computers Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong
2000	J	`jnl`	Star test: the theory and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
2000	A	`conf`	Wave Steered FSMs. DATE Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
2000	A*	`conf`	Wave-steering one-hot encoded FSMs. DAC Luca Macchiarulo, Malgorzata Marek-Sadowska
2000	C	`conf`	Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. ICCD Tong Xiao, Malgorzata Marek-Sadowska
1999	J	`jnl`	Circuit Optimization by Rewiring. IEEE Trans. Computers Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
1999	—	`conf`	Circuit clustering using graph coloring. ISPD Amit Singh, Malgorzata Marek-Sadowska
1999	—	`conf`	Crosstalk Reduction by Transistor Sizing. ASP-DAC Tong Xiao, Malgorzata Marek-Sadowska
1999	J	`jnl`	Crosstalk in VLSI interconnections. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
1999	J	`jnl`	Logic synthesis for engineering change. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
1999	Misc	`conf`	Modeling Crosstalk in Resistive VLSI Interconnections. VLSI Design Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
1999	J	`jnl`	Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. IEEE Trans. Computers Douglas Chang, Malgorzata Marek-Sadowska
1999	A	`conf`	STAR-ATPG: a high speed test pattern generator for large scan designs. ITC Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
1999	A*	`conf`	Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. DAC Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long
1999	—	`conf`	Wave pipelining YADDs-a feasibility study. CICC Arindam Mukherjee, Malgorzata Marek-Sadowska, Stephen I. Long
1998	J	`jnl`	A hybrid methodology for switching activities estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
1998	J	`jnl`	Cost-free scan: a low-overhead scan path design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
1998	A	`conf`	Functional Scan Chain Testing. DATE Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
1998	A	`conf`	Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. FPGA Douglas Chang, Malgorzata Marek-Sadowska
1998	J	`jnl`	Power Distribution Synthesis for VLSI. VLSI Design Ashok Vittal, Malgorzata Marek-Sadowska
1998	J	`jnl`	Test-point insertion: scan paths through functional logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1997	A*	`conf`	A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
1997	J	`jnl`	Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. IEEE Trans. Computers Chien-Chung Tsai, Malgorzata Marek-Sadowska
1997	A	`conf`	Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. FPGA Douglas Chang, Malgorzata Marek-Sadowska
1997	J	`jnl`	Crosstalk reduction for VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashok Vittal, Malgorzata Marek-Sadowska
1997	—	`conf`	Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. ISMVL Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
1997	—	`conf`	Decomposition of Multiple-Valued Relations . ISMVL Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
1997	J	`jnl`	Low-power buffered clock tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashok Vittal, Malgorzata Marek-Sadowska
1997	—	`conf`	Not necessarily more switches more routability [sic.]. ASP-DAC Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama
1997	J	`jnl`	On designing universal logic blocks and their application to FPGA design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chih-Chang Lin, Malgorzata Marek-Sadowska
1997	A*	`conf`	Post-Layout Logic Restructuring for Performance Optimization. DAC Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
1997	J	`jnl`	Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
1997	J	`jnl`	Routing for array-type FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Liang Wu, Malgorzata Marek-Sadowska
1997	A*	`conf`	STARBIST: Scan Autocorrelated Random Pattern Generation. DAC Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
1997	A	`conf`	Scan-Encoded Test Pattern Generation for BIST. ITC Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
1996	A*	`conf`	A New Hybrid Methodology for Power Estimation. DAC David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
1996	A	`conf`	Clock skew optimization for ground bounce control. ICCAD Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska
1996	A	`conf`	Fast Boolean optimization by rewiring. ICCAD Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
1996	J	`jnl`	Generalized Reed-Muller Forms as a Tool to Detect Symmetries. IEEE Trans. Computers Chien-Chung Tsai, Malgorzata Marek-Sadowska
1996	J	`jnl`	Graph based analysis of 2-D FPGA routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
1996	—	`conf`	Logic Synthesis for Testability. Great Lakes Symposium on VLSI Chien-Chung Tsai, Malgorzata Marek-Sadowska
1996	A*	`conf`	Multilevel Logic Synthesis for Arithmetic Functions. DAC Chien-Chung Tsai, Malgorzata Marek-Sadowska
1996	—	`conf`	Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares. ED&TC Shih-Chieh Chang, Malgorzata Marek-Sadowska
1996	J	`jnl`	Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1996	—	`conf`	Sequential Permissible Functions and their Application to Circuit Optimization. ED&TC Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
1996	J	`jnl`	Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
1996	A*	`conf`	Test Point Insertion: Scan Paths through Combinational Logic. DAC Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1995	A*	`conf`	An Efficient Algorithm for Local Don't Care Sets Calculation. DAC Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1995	A	`conf`	Circuit partitioning with logic perturbation. ICCAD David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
1995	A	`conf`	Cost-free scan: a low-overhead scan path design methodology. ICCAD Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995	A*	`conf`	Logic Synthesis for Engineering Change. DAC Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
1995	—	`conf`	Logic rectification and synthesis for engineering change. ASP-DAC Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995	A*	`conf`	Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. DAC Yu-Liang Wu, Malgorzata Marek-Sadowska
1995	A*	`conf`	Power Distribution Topology Design. DAC Ashok Vittal, Malgorzata Marek-Sadowska
1995	A*	`conf`	Power Optimal Buffered Clock Tree Design. DAC Ashok Vittal, Malgorzata Marek-Sadowska
1995	—	`conf`	Routing on regular segmented 2-D FPGAs. ASP-DAC Yu-Liang Wu, Malgorzata Marek-Sadowska
1995	J	`jnl`	The crossing distribution problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
1994	—	`conf`	An Efficient Router for 2-D Field Programmable Gate Arrays. EDAC-ETC-EUROASIC Yu-Liang Wu, Malgorzata Marek-Sadowska
1994	A*	`conf`	Boolean Matching Using Generalized Reed-Muller Forms. DAC Chien-Chung Tsai, Malgorzata Marek-Sadowska
1994	C	`conf`	Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. ISCAS Chien-Chung Tsai, Malgorzata Marek-Sadowska
1994	A*	`conf`	Layout Driven Logic Synthesis for FPGAs. DAC Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
1994	A*	`conf`	Minimal Delay Interconnect Design Using Alphabetic Trees. DAC Ashok Vittal, Malgorzata Marek-Sadowska
1994	—	`conf`	Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. EDAC-ETC-EUROASIC Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska
1994	—	`conf`	On computational complexity of a detailed routing problem in two dimensional FPGAs. Great Lakes Symposium on VLSI Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
1994	J	`jnl`	On the Verification of Function Equivalence with unknown Input Correspondence. J. Circuits Syst. Comput. David Ihsin Cheng, Malgorzata Marek-Sadowska
1994	A	`conf`	Perturb and simplify: multi-level boolean network optimizer. ICCAD Shih-Chieh Chang, Malgorzata Marek-Sadowska
1994	A	`conf`	Universal logic gate for FPGA design. ICCAD Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin
1993	—	`conf`	Efficient minimization algorithms for fixed polarity AND/XOR canonical networks. Great Lakes Symposium on VLSI Chien-Chung Tsai, Malgorzata Marek-Sadowska
1993	—	`conf`	Graph based analysis of FPGA routing. EURO-DAC Yu-Liang Wu, Malgorzata Marek-Sadowska
1993	—	`ch.`	Issues in Timing Driven Layout. Algorithmic Aspects of VLSI Layout Malgorzata Marek-Sadowska
1993	J	`jnl`	Stepwise equivalent conductance circuit simulation technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1992	Misc	`conf`	A New Accurate and Efficient Timing Simulator. VLSI Design Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
1992	J	`jnl`	Algorithm for wire sizing of Power and Ground Networks in VLSI Designs. J. Circuits Syst. Comput. Robi Dutta, Malgorzata Marek-Sadowska
1992	J	`jnl`	Switch box routing: a retrospective. Integr. Malgorzata Marek-Sadowska
1992	C	`conf`	Technology Mapping via Transformations of Function Graphs. ICCD Shih-Chieh Chang, Malgorzata Marek-Sadowska
1991	—	`conf`	A fast and efficient algorithm for determining fanout trees in large networks. EURO-DAC Shen Lin, Malgorzata Marek-Sadowska
1991	—	`conf`	SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. EURO-DAC Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
1991	A	`conf`	The Crossing Distribution Problem. ICCAD Malgorzata Marek-Sadowska, Majid Sarrafzadeh
1990	A*	`conf`	Delay and Area Optimization in Standard-Cell Design. DAC Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990	A	`conf`	Floorplanning with Pin Assignment. ICCAD Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
1990	C	`conf`	Pin assignment for improved performance in standard cell design. ICCD Malgorzata Marek-Sadowska, Shen P. Lin
1989	—	`conf`	Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. ICCAL Fillia Makedon, Malgorzata Marek-Sadowska
1989	A*	`conf`	Automatic Sizing of Power/Ground (P/G) Networks in VLSI. DAC Rajiv Dutta, Malgorzata Marek-Sadowska
1989	A	`conf`	Timing driven placement. ICCAD Malgorzata Marek-Sadowska, Shen Lin
1987	J	`jnl`	Pad Assignment for Power Nets in VLSI Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Malgorzata Marek-Sadowska
1985	A*	`conf`	Two-dimensional router for double layer layout. DAC Malgorzata Marek-Sadowska
1984	J	`jnl`	An Efficient Single-Row Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
1984	J	`jnl`	An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Malgorzata Marek-Sadowska
1984	J	`jnl`	Global Routing for Gate Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jeong-Tyng Li, Malgorzata Marek-Sadowska
1983	J	`jnl`	Single-Layer Routing for VLSI: Analysis and Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng