Malgorzata Chrzanowska-Jeske

75 papers A* 2A 1B 2C 14Journal 15Unranked 41
YearRankTypeTitle / Venue / Authors
2024 C conf
SERS-3DPlace: Ensemble Reinforcement Learning for 3D Monolithic Placement.
ISCAS
Abdullah Mansoor, Malgorzata Chrzanowska-Jeske
2022 C conf
RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing.
ISCAS
Abdullah Mansoor, Malgorzata Chrzanowska-Jeske
2021 J jnl
Fast Buffer Count Estimation in 3D IC Floorplanning.
IEEE Trans. Circuits Syst. II Express Briefs
Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske
2021 — conf
Fast Thermal Goodness Evaluation of a 3D-IC Floorplan.
ISQED
Satya K. Vendra, Malgorzata Chrzanowska-Jeske
2019 J jnl
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2018 C conf
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile.
ISCAS
Satya K. Vendra, Malgorzata Chrzanowska-Jeske
2016 — conf
Buffered Interconnects in 3D IC Layout Design.
SLIP
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2016 — conf
Performance optimization and power efficiency in 3D IC with buffer insertion scheme.
SoCC
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2016 — conf
Tutorial 2A: 3D integration - challenges and advantages.
SoCC
Malgorzata Chrzanowska-Jeske, Jürgen Becker
2015 C conf
Dynamic nets-to-TSVs assignment in 3D floorplanning.
ISCAS
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2014 — conf
3D floorplanning with nets-to-TSVs assignment.
ICECS
Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske
2014 — conf
Delay and power optimization with TSV-aware 3D floorplanning.
ISQED
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2014 — conf
Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes.
ICECS
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2014 — conf
TSVs in early layout design exploration for 3D ICs.
LASCAS
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2013 — conf
Fast floorplanning with placement constraints.
LASCAS
Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske
2013 C conf
Just because we teach it does not mean they use it: Case of programming skills.
FIE
Branimir Pejcinovic, Melinda Holtzman, Malgorzata Chrzanowska-Jeske, Phillip K. Wong
2013 — conf
TSV capacitance aware 3-D floorplanning.
3DIC
Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2012 — conf
Fast floorplanning for fixed-outline and nonrectangular regions.
ICECS
Mohammad A. Ahmed, Shantesh Pinge, Malgorzata Chrzanowska-Jeske
2012 C conf
Performance analysis of CNFET based circuits in the presence of fabrication imperfections.
ISCAS
Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra
2012 — conf
TSV stress-aware performance and reliability analysis.
ICECS
Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske
2011 J jnl
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs.
IEEE Trans. Very Large Scale Integr. Syst.
Rajeev K. Nain, Malgorzata Chrzanowska-Jeske
2010 — conf
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.
NANOARCH
Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2010 — conf
Yield enhancement by tube redundancy in CNFET-based circuits.
ICECS
Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2010 — conf
Yield improvement of 3D ICs in the presence of defects in through signal vias.
ISQED
Rajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske
2009 C conf
Placement-aware 3D Floorplanning.
ISCAS
Rajeev K. Nain, Malgorzata Chrzanowska-Jeske
2008 C conf
Carbon nanotube circuit design choices in the presence of metallic tubes.
ISCAS
Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2008 C conf
Optimization of active circuits for substrate noise suppression.
ISCAS
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2008 — conf
Rectangular 3D wirelength distribution models.
ICECS
Rajeev K. Nain, Rajarshi Ray, Malgorzata Chrzanowska-Jeske
2007 J jnl
A novel net-degree distribution model and its application to floorplanning benchmark generation.
Integr.
Tao Wan, Malgorzata Chrzanowska-Jeske
2007 J jnl
Supply current spectrum estimation of digital cores at early design.
IET Circuits Devices Syst.
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2006 C conf
Estimation of supply current spectrum for early noise evaluation.
ISCAS
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2006 J jnl
Linear cofactor relationships in Boolean functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2006 A* conf
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
DAC
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2006 J jnl
Using simulation and satisfiability to compute flexibilities in Boolean networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2005 — conf
Considering layout for test scheduling of core-based SoCs.
ICECS
Yu Xia, Malgorzata Chrzanowska-Jeske
2005 — conf
Detecting support-reducing bound sets using two-cofactor symmetries.
ASP-DAC
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2005 — conf
Modeling of substrate noise block properties for early prediction.
ISCAS (3)
Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske
2005 — conf
Substrate noise modeling in early floorplanning of MS-SOCs.
ASP-DAC
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske, Jin S. Zhang
2005 — conf
Synthesis for regularity using decision diagrams [logic IC synthesis and layout].
ISCAS (5)
Malgorzata Chrzanowska-Jeske, Alan Mishchenko
2004 — conf
Generating random benchmark circuits for floorplanning.
ISCAS (5)
Tao Wan, Malgorzata Chrzanowska-Jeske
2004 — conf
Prediction of interconnect net-degree distribution based on Rent's rule.
SLIP
Tao Wan, Malgorzata Chrzanowska-Jeske
2004 — conf
Substrate noise optimization in early floorplanning for mixed signal SOCs.
SoCC
Grzegorz Blakiewicz, Marcin Jeske, Malgorzata Chrzanowska-Jeske
2004 — conf
Substrate noise-aware floorplanning for mixed-signal SOCs.
ISCAS (2)
Marcin Jeske, Grzegorz Blakiewicz, Malgorzata Chrzanowska-Jeske, Benyi Wang
2003 J jnl
Board-level multiterminal net assignment for the partial cross-bar architecture.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
2003 B conf
Core-based SoC test scheduling using evolutionary algorithm.
IEEE Congress on Evolutionary Computation
Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang
2003 — conf
Floorplanning with performance-based clustering.
ISCAS (4)
Malgorzata Chrzanowska-Jeske, Benyi Wang, Garrison W. Greenwood
2003 — conf
Graph-based approach to evaluate net routability of a floorplan.
ISCAS (5)
Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske
2003 J jnl
Integrated floorplanning with buffer/channel insertion for bus-based designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
2003 A conf
Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.
ICCAD
Yu Xia, Malgorzata Chrzanowska-Jeske, Benyi Wang, Marcin Jeske
2002 — conf
Board-level multiterminal net assignment.
ACM Great Lakes Symposium on VLSI
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
2002 B conf
Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules.
IEEE Congress on Evolutionary Computation
Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood, Benyi Wang
2002 — conf
ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules.
ICECS
Benyi Wang, Malgorzata Chrzanowska-Jeske, Garrison W. Greenwood
2002 J jnl
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts.
VLSI Design
Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler
2002 J jnl
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs.
VLSI Design
Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski
2002 — conf
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.
ISPD
Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
2001 — conf
A global approach to the variable ordering problem in PSBDDs.
ISCAS (5)
Wei Wang, Malgorzata Chrzanowska-Jeske
2001 — conf
Generalized symmetric variables.
ICECS
Malgorzata Chrzanowska-Jeske
2001 C conf
Regular Realization of Symmetric Functions Using Reversible Logic.
DSD
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
2000 — conf
Disjunctive Decomposition of Switching Functions Using Symmetry Information.
SBCCI
Malgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske
1999 — conf
Generalized symmetric and generalized pseudo-symmetric functions.
ICECS
Malgorzata Chrzanowska-Jeske
1999 J jnl
Logic Synthesis for a Regular Layout.
VLSI Design
Malgorzata Chrzanowska-Jeske, Yang Xu, Marek A. Perkowski
1999 — conf
Regular symmetric arrays for non-symmetric functions.
ISCAS (1)
Malgorzata Chrzanowska-Jeske
1998 — conf
Variable ordering for regular layout representation.
ICECS
Malgorzata Chrzanowska-Jeske, Yang Xu
1996 — conf
Synthesis approach to multi-level regular representation for combinational circuits.
ICECS
Malgorzata Chrzanowska-Jeske, Chungping Guo
1995 J jnl
A New Design Methodology for Two-Dimensional Logic Arrays.
VLSI Design
Ning Song, Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi
1995 — conf
Layout synthesis for datapath designs.
EURO-DAC
Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe
1995 J jnl
Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions.
VLSI Design
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi, Ingo Schäfer
1995 — conf
Tree restructuring approach to mapping problem in cellular-architecture FPGAs.
EURO-DAC
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Naveen Buddi
1994 A* conf
A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays.
DAC
Andisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski
1994 J jnl
An Exact Solution to the Fitting Problem in the Application Specific State Machine Device.
J. Circuits Syst. Comput.
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Edmund Pierzchala, Alan J. Coppola
1994 — conf
Multiple-Valued-Input TANT Networks.
ISMVL
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske
1994 C conf
Output Column Folding for Cellular-Architecture FPGAs.
ISCAS
Ning Song, Malgorzata Chrzanowska-Jeske
1993 C conf
An Architecture-driven Approach for the Fitting Problem in an Application-specific EPLD.
ISCAS
Malgorzata Chrzanowska-Jeske, Steffen Goller, Ingo Schäfer
1993 — conf
Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device.
EURO-DAC
Malgorzata Chrzanowska-Jeske, Steffen Goller
1990 C conf
Minimization of multioutput TANT networks for unlimited fan-in network model.
ICCD
Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Tuhar Shah