Maksim Jenihhin

172 papers A 3B 8C 38Misc 4Journal 58Unranked 59

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Adaptive and efficient federated distillation with selective homomorphic encryption for edge AI. Expert Syst. Appl. Dadmehr Rahbari, Masoud Daneshtalab, Maksim Jenihhin
2026	J	`jnl`	DART: Input-Difficulty-AwaRe Adaptive Threshold for Early-Exit DNNs. CoRR Parth Patne, Mahdi Taheri, Christian Herglotz, Maksim Jenihhin, Milos Krstic, Michael Hübner
2026	—	`conf`	Investigating the Impact of Soft Errors in GPU-Accelerated Sparse DNNs. LASCAS Mohammad Hasan Ahmadilivani, Josie E. Rodriguez Condia, Maksim Jenihhin, Matteo Sonza Reorda
2026	J	`jnl`	Progressive Training of Hybrid Clipped Rectified Linear Unit for Resilient Convolution Neural Networks. IEEE Access Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab
2026	—	`conf`	Reliability Assessment of Deep Neural Networks and Accelerators Across Design Stages. LATS Mohammad Hasan Ahmadilivani, Natalia Cherezova, Michael Glaß, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Letícia Maria Veiras Bolzani Poehls, Jaan Raik, Lucas Roquet, Fernando Fernandes dos Santos, Felipe Augusto da Silva, Matteo Sonza Reorda, Alessandro Veronesi, Ernesto Cristopher Villegas Castillo, Josie E. Rodriguez Condia
2026	J	`jnl`	SPARQ: Spiking Early-Exit Neural Networks for Energy-Efficient Edge AI. CoRR Parth Patne, Mahdi Taheri, Ali Mahani, Maksim Jenihhin, Reza Mahani, Christian Herglotz
2025	—	`conf`	Adaptive Fault Resilience for Early-Exit DNNs. ITC-Asia Rama Mounika Kodamanchili, Natalia Cherezova, Mahdi Taheri, Maksim Jenihhin
2025	J	`jnl`	An Efficient Architecture for Edge AI Federated Learning With Homomorphic Encryption. IEEE Access Dadmehr Rahbari, Masoud Daneshtalab, Maksim Jenihhin
2025	—	`conf`	AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier. ISVLSI Ahsan Rafiq, Alberto Bosio, Salvatore Pappalardo, Maksim Jenihhin
2025	—	`conf`	Does Fault Tolerance Safeguard DNNs Against Bitfiip Attacks? A Case Study. DFT Mohammad Hasan Ahmadilivani, Yuto Kobayashi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	J	`jnl`	FORTALESA: Fault-Tolerant Reconfigurable Systolic Array for DNN Inference. CoRR Natalia Cherezova, Artur Jutman, Maksim Jenihhin
2025	—	`conf`	GENIE: GENetIc Algorithm-Based REliability Assessment Methodology for Deep Neural Networks. ICCAI Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Christian Herglotz, Maksim Jenihhin
2025	C	`conf`	RL-Agent-based Early-Exit DNN Architecture Search Framework. DDECS Mahdi Taheri, Parth Patne, Natalia Cherezova, Ali Mahani, Christian Herglotz, Maksim Jenihhin
2025	J	`jnl`	Reliability-Aware Hyperparameter Optimization for ANN-to-SNN Conversion. WiPiEC Journal Saeed Sharifian Moghimi Moghaddam, Mahdi Taheri, Vahid Rashtchi, Ali Azarpeyvand, Christian Herglotz, Maksim Jenihhin
2025	—	`conf`	Reliability-Aware Performance Optimization of DNN HW Accelerators Through Heterogeneous Quantization. LATS Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Christian Herglotz, Maksim Jenihhin
2025	J	`jnl`	SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators. J. Circuits Syst. Comput. Salvatore Pappalardo, Nicolò Bellarmino, Bastien Deveautour, Alberto Bosio, Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2025	C	`conf`	SHIELD: PSO-Based Hardware Trojan Detection for Efficient and Low-Cost Defense. IOLTS Mostafa Hosseini, Ali Azarpeyvand, Mahdi Taheri, Tara Ghasempouri, Maksim Jenihhin
2025	—	`conf`	XMULT: An Energy-Efficient Design of Approximate Multiplier. DSN-W Ahsan Rafiq, Maksim Jenihhin
2024	J	`jnl`	A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. ACM Comput. Surv. Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	B	`conf`	AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. ETS Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2024	J	`jnl`	AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators. CoRR Mahdi Taheri, Natalia Cherezova, Samira Nazari, Ahsan Rafiq, Ali Azarpeyvand, Tara Ghasempouri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2024	C	`conf`	Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. IOLTS Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	J	`jnl`	Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning. CoRR Mohammad Hasan Ahmadilivani, Seyedhamidreza Mousavi, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	J	`jnl`	DeepVigor+: Scalable and Accurate Semi-Analytical Fault Resilience Analysis for Deep Neural Network. CoRR Mohammad Hasan Ahmadilivani, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2024	—	`conf`	Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. ISQED Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik
2024	J	`jnl`	Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators. CoRR Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik
2024	—	`conf`	FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs. ATS Samira Nazari, Mahdi Taheri, Ali Azarpeyvand, Mohsen Afsharchi, Tara Ghasempouri, Christian Herglotz, Masoud Daneshtalab, Maksim Jenihhin
2024	C	`conf`	Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. VLSI-SoC Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin
2024	—	`conf`	IJTAG-compatible Symptom-based SEU Monitors for FPGA DNN Accelerators. DTTIS Natalia Cherezova, Maksim Jenihhin, Artur Jutman
2024	—	`conf`	Keynote: Cost-Efficient Reliability for Edge-AI Chips. LATS Maksim Jenihhin, Mahdi Taheri, Natalia Cherezova, Mohammad Hasan Ahmadilivani, Hardi Selg, Artur Jutman, Konstantin Shibin, Anton Tsertov, Sergei Devadze, Rama Mounika Kodamanchili, Ahsan Rafiq, Jaan Raik, Masoud Daneshtalab
2024	J	`jnl`	ProAct: Progressive Training for Hybrid Clipped Activation Function to Enhance Resilience of DNNs. CoRR Seyedhamidreza Mousavi, Mohammad Hasan Ahmadilivani, Jaan Raik, Maksim Jenihhin, Masoud Daneshtalab
2024	J	`jnl`	Reliability-Critical Computation Offloading in UAV Swarms. IEEE Syst. J. Dadmehr Rahbari, Foisal Ahmed, Maksim Jenihhin, Muhammad Mahtab Alam, Yannick Le Moullec
2024	C	`conf`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	J	`jnl`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	—	`conf`	Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs. DFT Hardi Selg, Konstantin Shibin, Anton Tsertov, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
2024	Misc	`conf`	Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola
2024	—	`book`	Structural Decision Diagrams in Digital Test - Theory and Applications Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman
2023	C	`ed.`	26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023, Tallinn, Estonia, May 3-5, 2023 DDECS Maksim Jenihhin, Hana Kubátová, Nele Metens, Jaan Raik, Foisal Ahmed, Jan Belohoubek
2023	J	`jnl`	A Novel Fault-Tolerant Logic Style with Self-Checking Capability. CoRR Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin
2023	J	`jnl`	A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	C	`conf`	APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. DDECS Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik
2023	J	`jnl`	APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors. CoRR Mahdi Taheri, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik
2023	J	`jnl`	An automated method for mining high-quality assertion sets. Microprocess. Microsystems Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri
2023	—	`conf`	Analyzing Side-Channel Attack Vulnerabilities at RTL. LATS Xinhui Lai, Maksim Jenihhin
2023	J	`jnl`	Applying RIS-Based Communication for Collaborative Computing in a Swarm of Drones. IEEE Access Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin
2023	—	`conf`	DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. ISQED Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper
2023	J	`jnl`	DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. CoRR Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper
2023	B	`conf`	DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment. ETS Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	J	`jnl`	DeepVigor: Vulnerability Value Ranges and Factors for DNNs' Reliability Assessment. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	—	`conf`	Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. AICAS Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	J	`jnl`	Enhancing Fault Resilience of QNNs by Selective Neuron Splitting. CoRR Mohammad Hasan Ahmadilivani, Mahdi Taheri, Jaan Raik, Masoud Daneshtalab, Maksim Jenihhin
2023	—	`conf`	Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. LATS Foisal Ahmed, Maksim Jenihhin
2023	J	`jnl`	Holistic IJTAG-based External and Internal Fault Monitoring in UAVs. CoRR Foisal Ahmed, Maksim Jenihhin
2023	C	`conf`	ML-Based Online Design Error Localization for RISC-V Implementations. IOLTS Hardi Selg, Maksim Jenihhin, Peeter Ellervee, Jaan Raik
2023	—	`conf`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. DFT Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2023	J	`jnl`	On-Chip Sensors Data Collection and Analysis for SoC Health Management. CoRR Konstantin Shibin, Maksim Jenihhin, Artur Jutman, Sergei Devadze, Anton Tsertov
2023	Misc	`conf`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2023	J	`jnl`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2023	J	`jnl`	Unsupervised Recycled FPGA Detection Using Symmetry Analysis. CoRR Tanvir Ahmad Tarique, Foisal Ahmed, Maksim Jenihhin, Liakot Ali
2022	C	`conf`	A Novel Fault-Tolerant Logic Style with Self-Checking Capability. IOLTS Mahdi Taheri, Saeideh Sheikhpour, Ali Mahani, Maksim Jenihhin
2022	J	`jnl`	A Survey on UAV Computing Platforms: A Hardware Reliability Perspective. Sensors Foisal Ahmed, Maksim Jenihhin
2022	—	`conf`	High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2022	C	`conf`	MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi
2022	—	`conf`	On BTI Aging Rejuvenation in Memory Address Decoders. LATS Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui
2022	J	`jnl`	On BTI Aging Rejuvenation in Memory Address Decoders. CoRR Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui
2021	—	`conf`	A Methodology for Automated Mining of Compact and Accurate Assertion Sets. NorCAS Mohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri
2021	J	`jnl`	Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2021	—	`conf`	Edge-to-Fog Collaborative Computing in a Swarm of Drones. MEDI Workshops Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin
2021	J	`jnl`	Fast and Fair Computation Offloading Management in a Swarm of Drones Using a Rating-Based Federated Learning Approach. IEEE Access Dadmehr Rahbari, Muhammad Mahtab Alam, Yannick Le Moullec, Maksim Jenihhin
2021	—	`conf`	Gate-Level Graph Representation Learning: A Step Towards the Improved Stuck-at Faults Analysis. ISQED Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin, Thomas Lange, Maximilien Glorieux
2021	C	`conf`	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar
2021	—	`conf`	JÄNES: A NAS Framework for ML-based EDA Applications. DFT Hardi Selg, Maksim Jenihhin, Peeter Ellervee
2021	J	`jnl`	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2021	—	`conf`	Modeling Soft-Error Reliability Under Variability. DFT Aneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu
2021	C	`conf`	On Antagonism Between Side-Channel Security and Soft-Error Reliability in BNN Inference Engines. VLSI-SoC Xinhui Lai, Thomas Lange, Aneesh Balakrishnan, Dan Alexandrescu, Maksim Jenihhin
2021	J	`jnl`	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
2021	J	`jnl`	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. CoRR Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2020	A	`conf`	A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs. DATE Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback, Maksim Jenihhin, Mottaqiallah Taouil, Said Hamdioui
2020	J	`jnl`	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2020	J	`jnl`	Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	—	`conf`	Composing Graph Theory and Deep Neural Networks to Evaluate SEU Type Soft Error Effects. MECO Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2020	C	`conf`	Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. VLSI-SOC Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul
2020	J	`jnl`	Early RTL Analysis for SCA Vulnerability in Fuzzy Extractors of Memory-Based PUF Enabled Devices. CoRR Xinhui Lai, Maksim Jenihhin, Georgios N. Selimis, Sven Goossens, Roel Maes, Kolin Paul
2020	J	`jnl`	Efficient Fault Injection based on Dynamic HDL Slicing Technique. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2020	J	`jnl`	High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	C	`conf`	Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	J	`jnl`	New categories of Safe Faults in a processor-based Embedded System. CoRR Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2020	J	`jnl`	PASCAL: Timing SCA Resistant Design and Verification Flow. CoRR Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
2020	A	`conf`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. DATE Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2020	C	`conf`	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. IOLTS Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
2020	Misc	`conf`	Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks. VTS Felipe Augusto da Silva, Ahmet Cagri Bagbaba, Annachiara Ruospo, Riccardo Mariani, Ghani Kanawati, Ernesto Sánchez, Matteo Sonza Reorda, Maksim Jenihhin, Said Hamdioui, Christian Sauer
2020	—	`conf`	Wafer-Level Die Re-Test Success Prediction Using Machine Learning. LATS Hardi Selg, Maksim Jenihhin, Peeter Ellervee
2019	—	`conf`	Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing. NORCAS Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2019	—	`conf`	An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
2019	J	`jnl`	An optimization framework for dynamic pipeline management in computing systems. Comput. Electr. Eng. Syed Rameez Naqvi, Anjum Zahid, Lina Sawalha, Syed Saud Naqvi, Tallha Akram, Sajjad Ali Haider, Kumar Yelamarthi, Maksim Jenihhin
2019	C	`conf`	Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
2019	—	`conf`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. DFT Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	J	`jnl`	Challenges of Reliability Assessment and Enhancement in Autonomous Systems. CoRR Maksim Jenihhin, Matteo Sonza Reorda, Aneesh Balakrishnan, Dan Alexandrescu
2019	C	`conf`	Efficient Fault Injection based on Dynamic HDL Slicing Technique. IOLTS Ahmet Cagri Bagbaba, Maksim Jenihhin, Jaan Raik, Christian Sauer
2019	B	`conf`	High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	C	`conf`	Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	—	`conf`	Mixed-level identification of fault redundancy in microprocessors. LATS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	Mixed-level identification of fault redundancy in microprocessors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	—	`conf`	Modeling Gate-Level Abstraction Hierarchy Using Graph Convolutional Neural Networks to Predict Functional De-Rating Factors. AHS Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2019	C	`conf`	New categories of Safe Faults in a processor-based Embedded System. DDECS Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2019	C	`conf`	On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. VLSI-SoC Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy, Maksim Jenihhin
2019	—	`conf`	On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	C	`conf`	PASCAL: Timing SCA Resistant Design and Verification Flow. IOLTS Xinhui Lai, Maksim Jenihhin, Jaan Raik, Kolin Paul
2019	J	`jnl`	RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems. CoRR Maksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, Christian Sauer, Anton Klotz, Michael Hübner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka
2019	—	`conf`	Software-Based Mitigation for Memory Address Decoder Aging. LATS Daniel H. P. Kraak, Cemil Cem Gürsoy, Innocent O. Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui
2019	—	`conf`	The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications. NORCAS Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin
2019	J	`jnl`	Towards Multidimensional Verification: Where Functional Meets Non-Functional. CoRR Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
2019	C	`conf`	True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin
2019	J	`jnl`	Understanding multidimensional verification: Where functional meets non-functional. Microprocess. Microsystems Xinhui Lai, Aneesh Balakrishnan, Thomas Lange, Maksim Jenihhin, Tara Ghasempouri, Jaan Raik, Dan Alexandrescu
2018	—	`ed.`	2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018 NORCAS Jari Nurmi, Peeter Ellervee, Juri Mihhailov, Maksim Jenihhin, Kalle Tammemäe
2018	J	`jnl`	Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
2018	—	`conf`	Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
2018	C	`conf`	QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. DDECS Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
2018	—	`conf`	RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality. EWME Heinrich Theodor Vierhaus, Maksim Jenihhin, Matteo Sonza Reorda
2018	C	`conf`	Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey
2018	—	`conf`	Timing-critical path analysis with structurally synthesized BDDs. MECO Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
2018	—	`conf`	Towards Multidimensional Verification: Where Functional Meets Non-Functional. NORCAS Maksim Jenihhin, Xinhui Lai, Tara Ghasempouri, Jaan Raik
2018	C	`conf`	Upgrading QoSinNoC: Efficient Routing for Mixed-Criticality Applications and Power Analysis. VLSI-SoC Serhiy Avramenko, Siavoosh Payandeh Azad, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin
2017	C	`conf`	A scalable technique to identify true critical paths in sequential circuits. DDECS Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
2017	A	`conf`	BASTION: Board and SoC test instrumentation for ageing and no failure found. DATE Artur Jutman, Christophe Lotz, Erik Larsson, Matteo Sonza Reorda, Maksim Jenihhin, Jaan Raik, Hans G. Kerkhoff, Rene Krenz-Baath, Piet Engelke
2017	Misc	`conf`	Multi-Fragment Markov Model Guided Online Test Generation for MPSoC. ICTERI Jüri Vain, Leonidas Tsiopoulos, Vyacheslav S. Kharchenko, Apneet Kaur, Maksim Jenihhin, Jaan Raik
2016	C	`conf`	Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
2016	—	`conf`	Gate-level modelling of NBTI-induced delays under process variations. LATS Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2016	J	`jnl`	Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
2016	—	`conf`	Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
2016	—	`conf`	Universal mitigation of NBTI-induced aging by design randomization. EWDTS Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan
2015	—	`conf`	FSMD RTL design manipulation for clock interface abstraction. ICACCI Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2015	—	`conf`	Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	C	`conf`	SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	C	`conf`	SystemC-Based Loose Models for Simulation Speed-Up by Abstraction of RTL IP Cores. DDECS Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2014	J	`jnl`	Automated Design Error Localization in RTL Designs. IEEE Des. Test Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2014	B	`conf`	Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
2014	—	`conf`	Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti
2013	—	`conf`	Assessment of diagnostic test for automated bug localization. LATW Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2013	J	`jnl`	Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
2013	C	`conf`	Extensible open-source framework for translating RTL VHDL IP cores to SystemC. DDECS Syed Saif Abrar, Maksim Jenihhin, Jaan Raik
2013	C	`conf`	Identifying NBTI-Critical Paths in Nanoscale Logic. DSD Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls
2013	—	`conf`	Performance analysis of cosimulating processor core in VHDL and SystemC. ICACCI Syed Saif Abrar, Maksim Jenihhin, Jaan Raik, Shyam Kiran A., C. Babu
2012	C	`conf`	A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov
2012	B	`conf`	Combining dynamic slicing and mutation operators for ESL correction. ETS Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi
2012	—	`conf`	Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2012	C	`ed.`	IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012 DDECS Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin
2012	J	`jnl`	Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
2012	—	`conf`	Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2012	J	`jnl`	On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2012	—	`conf`	PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov
2011	—	`conf`	Automated test bench generation for high-level synthesis flow ABELITE. EWDTS Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov
2011	B	`conf`	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
2011	C	`conf`	EEG Analyzer prototype based on FPGA. ISPA Maksim Jenihhin, Maksim Gorev, Vadim Pesonen, Dmitri Mihhailov, Peeter Ellervee, Hiie Hinrikus, Maie Bachmann, Jaanus Lass
2011	—	`conf`	Mutation analysis for SystemC designs at TLM. LATW Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2010	—	`conf`	An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova
2010	C	`conf`	Constraint-based test pattern generation at the Register-Transfer Level. DDECS Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko
2010	—	`conf`	Mutation analysis with high-level decision diagrams. LATW Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi
2009	—	`conf`	High-Level Decision Diagrams based coverage metrics for verification and test. LATW Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar
2009	J	`jnl`	PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2008	C	`conf`	Code Coverage Analysis using High-Level Decision Diagrams. DDECS Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee
2008	C	`conf`	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz
2008	—	`conf`	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee
2008	J	`jnl`	Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin
2008	B	`conf`	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. ETS Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2007	C	`conf`	Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
2006	J	`jnl`	Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
2004	—	`conf`	Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA Raimund Ubar, Maksim Jenihhin
2003	—	`conf`	Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
2003	—	`conf`	Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin