Makoto Yabuuchi

37 papers A 1Journal 11Unranked 25

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 3-nm FinFET 563-kbit 35.5-Mbit/mm IEEE J. Solid State Circuits Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Kazuto Mizutani, Masaya Hamada, Yuichiro Ishii, Yen Chi Chou, Jun Cheng Liu, Chien-yu Huang, Kang-Hui Peng, Yu-Hao Hsu, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024	J	`jnl`	A 3-nm FinFET 27.6-Mbit/mm IEEE J. Solid State Circuits Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2024	—	`conf`	A 3nm Fin-FET 19.87-Mbit/mm VLSI Technology and Circuits Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2023	—	`conf`	A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. VLSI Technology and Circuits Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
2021	J	`jnl`	An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi
2020	—	`conf`	A 29.2 Mb/mm VLSI Circuits Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka
2020	—	`conf`	A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. VLSI Circuits Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka
2019	—	`conf`	A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm VLSI Circuits Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose
2019	—	`conf`	Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process. IRPS Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa, Makoto Yabuuchi, Yasumasa Tsukamoto, Koji Shibutani
2018	—	`conf`	12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. VLSI Circuits Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka
2018	—	`conf`	40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. A-SSCC Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii
2018	J	`jnl`	A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. IEEE Trans. Very Large Scale Integr. Syst. Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Tanaka, Koji Nii
2016	—	`conf`	A 5.92-Mb/mm A-SSCC Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii
2016	—	`conf`	A 6.05-Mb/mm VLSI Circuits Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii
2015	—	`conf`	1.8 Mbit/mm VLSIC Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii
2014	—	`conf`	13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ISSCC Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii
2014	J	`jnl`	28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. IEEE Trans. Very Large Scale Integr. Syst. Yukiko Umemoto, Koji Nii, Jiro Ishikawa, Makoto Yabuuchi, Kazuyoshi Okamoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Tetsuya Matsumura, Kazutaka Mori, Kazumasa Yanagisawa
2014	J	`jnl`	A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato
2014	—	`conf`	Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. ISQED Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii
2013	—	`conf`	A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure. CICC Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Miki Tanaka, Shinji Tanaka, Koji Nii
2013	—	`conf`	A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
2012	—	`conf`	A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki
2012	—	`conf`	A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. Asian Test Symposium Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto
2012	—	`conf`	A stable chip-ID generating physical uncloneable function using random address errors in SRAM. SoCC Hidehiro Fujiwara, Makoto Yabuuchi, Yasumasa Tsukamoto, Hirofumi Nakano, Toru Owada, Hiroyuki Kawai, Koji Nii
2012	—	`conf`	Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application. ISQED Yasumasa Tsukamoto, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Changhwan Shin, Tsu-Jae King Liu
2011	A	`conf`	A dynamic body-biased SRAM with asymmetric halo implant MOSFETs. ISLPED Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Shigeki Tawa, Koji Maekawa, Motoshige Igarashi, Koji Nii
2010	—	`conf`	A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias. ISSCC Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Yuuichi Hirano, Toshiaki Iwamatsu, Yuji Kihara
2010	—	`conf`	Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto
2009	J	`jnl`	Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
2008	J	`jnl`	A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
2008	J	`jnl`	A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2008	J	`jnl`	A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
2007	J	`jnl`	A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
2007	—	`conf`	A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara