Makoto Sugihara

26 papers A 3C 3Misc 1Journal 14Unranked 5
YearRankTypeTitle / Venue / Authors
2014 J jnl
Minimization of the Fabrication Cost for a Bridged-Bus-Based TDMA System under Hard Real-Time Constraints.
IEICE Trans. Inf. Syst.
Makoto Sugihara
2013 J jnl
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications.
Inf. Media Technol.
Makoto Sugihara, Akihito Iwanaga
2013 J jnl
Minimization of FlexRay Bus Bandwidth for Hard Real-Time Applications.
J. Inf. Process.
Makoto Sugihara, Akihito Iwanaga
2013 J jnl
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints.
Inf. Media Technol.
Makoto Sugihara, Akihito Iwanaga
2013 J jnl
Slot Multiplexing Optimization for Minimizing the Operating Frequency of a FlexRay Bus under Hard Real-time Constraints.
J. Inf. Process.
Makoto Sugihara, Akihito Iwanaga
2011 J jnl
A Dynamic Continuous Signature Monitoring Technique for Reliable Microprocessors.
IEICE Trans. Electron.
Makoto Sugihara
2010 J jnl
Character-Size Optimization for Reducing the Number of EB Shots of MCC Lithographic Systems.
IEICE Trans. Electron.
Makoto Sugihara
2010 C conf
Dynamic Control Flow Checking Technique for Reliable Microprocessors.
DSD
Makoto Sugihara
2010 J jnl
On Synthesizing a Reliable Multiprocessor for Embedded Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Makoto Sugihara
2009 C conf
Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints.
DSD
Makoto Sugihara
2009 J jnl
Reliability Inherent in Heterogeneous Multiprocessor Systems and Task Scheduling for Ameliorating Their Reliability.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Makoto Sugihara
2008 J jnl
Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Makoto Sugihara, Yusuke Matsunaga, Kazuaki J. Murakami
2008 J jnl
Reliable Cache Architectures and Task Scheduling for Multiprocessor Systems.
IEICE Trans. Electron.
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2008 — conf
SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems.
ISQED
Makoto Sugihara
2007 J jnl
Architectural-Level Soft-Error Modeling for Estimating Reliability of Computer Systems.
IEICE Trans. Electron.
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2007 A conf
Task scheduling for reliable cache architectures of multiprocessor systems.
DATE
Makoto Sugihara, Tohru Ishihara, Kazuaki J. Murakami
2007 J jnl
Technology Mapping Technique for Increasing Throughput of Character Projection Lithography.
IEICE Trans. Electron.
Makoto Sugihara, Kenta Nakamura, Yusuke Matsunaga, Kazuaki J. Murakami
2006 — conf
A Simulation-Based Soft Error Estimation Methodology for Computer Systems.
ISQED
Makoto Sugihara, Tohru Ishihara, Masanori Muroyama, Koji Hashimoto
2006 C conf
A character size optimization technique for throughput enhancement of character projection lithography.
ISCAS
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2006 J jnl
Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment.
IEICE Trans. Electron.
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2005 — conf
Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems.
SoC
Makoto Sugihara, Taiga Takata, Kenta Nakamura, Ryoichi Inanami, Hiroaki Hayashi, Katsumi Kishimoto, Tetsuya Hasebe, Yukihiro Kawano, Yusuke Matsunaga, Kazuaki J. Murakami, Katsuya Okumura
2004 — conf
Practical Test Architecture Optimization for System-on-a-Chip under Floorplanning Constraints.
ISVLSI
Makoto Sugihara, Kazuaki J. Murakami, Yusuke Matsunaga
2002 — conf
Optimization of Test Accesses with a Combined BIST and External Test Scheme.
ASP-DAC/VLSI Design
Makoto Sugihara, Hiroto Yasuura
2000 A conf
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach.
DATE
Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
2000 Misc conf
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
PDPTA
Hiroshi Date, Vikram Iyengar, Krishnendu Chakrabarty, Makoto Sugihara
1998 A conf
A novel test methodology for core-based system LSIs and a testing time minimization problem.
ITC
Makoto Sugihara, Hiroshi Date, Hiroto Yasuura