Makoto Nagata - RankMe

197 papers A* 4A 3B 3C 7Misc 3Journal 92Unranked 85

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	29.5 A Sub-Gram Individual Plant Stress Sensor Tag for Smart Farming. ISSCC Daiki Nitto, Keishi Yanase, Yui Fujisawa, Jun Shiomi, Yoshihiro Midoh, Takuya Wadatsumi, Makoto Nagata, Ahmet Öncü, Constantine Sideris, Chetphilin Suriyasak, Yushi Ishibashi, Noriyuki Miura
2026	J	`jnl`	Effect of blending poly(2,6-dimethyl-1,4-phenylene sulfide) resin bearing vinyl groups on printed wiring boards. IEICE Electron. Express Daisuke Ito, Shinsuke Ishikawa, Hidenori Fujimoto, Akihiko Happoya, Makoto Nagata
2025	J	`jnl`	A 20-GHz Low-Noise RF Pulse Generator for Silicon Quantum Computer with 137.4-fs Jitter. IEICE Trans. Electron. Takayasu Norimatsu, Yusuke Wachi, Takuji Miki, Yusuke Kanno, Ryozo Takahashi, Takashi Ogawa, Takeru Utsugi, Tomonori Sekiguchi, Makoto Nagata, Hiroyuki Mizuno
2025	J	`jnl`	Cryogenic CMOS Analog Circuits and Chip Packaging Techniques towards Large-Scale Silicon Quantum Computers. IEICE Trans. Electron. Takuji Miki, Misato Taguchi, Makoto Nagata
2025	—	`conf`	ML-EMFI: A Machine Learning-Driven Pre-Silicon Electromagnetic Fault Injection Security Evaluation for Robust IC Design. HOST Pantha Protim Sarker, Tianze Kan, Jingchen Liang, Ozgur Tuncer, Bo He, Zelin Lu, Sudarshan Mallu, Lang Lin, Norman Chang, Rikuu Hasegawa, Kazuki Monta, Makoto Nagata, Farimah Farahmandi, Mark Tehranipoor
2024	—	`conf`	A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation. AsianHOST Kazuki Monta, Takafumi Oki, Rikuu Hasegawa, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Norman Chang
2024	—	`conf`	A cryogenic pulse shaper for spin qubit control utilizing 1ns-time-resolution ADCs on an active silicon interposer operating at sub-100 mK temperatures. A-SSCC Ryozo Takahashi, Yusuke Kanno, Takuji Miki, Nobuhiro Kusuno, Hiroyuki Mizuno, Makoto Nagata
2024	—	`conf`	Accuracy of GPS Positioning Measurements in response to Electromagnetic Noise Characteristics. EMC Compo Hiraku Uehara, Koh Watanabe, Sosuke Ashida, Yushi Mitsuya, Satoshi Tanaka, Makoto Nagata
2024	J	`jnl`	Electromagnetic Interference With the Mobile Communication Devices in Unmanned Aerial Vehicles and Its Countermeasures. IEEE Access Koh Watanabe, Ryota Sakai, Satoshi Tanaka, Makoto Nagata, Hideki Osaka, Atsushi Nakamura, Ifong Wu, Yasushi Matsumoto, Kaoru Gotoh
2024	C	`conf`	Fault Injection Attacks Exploiting High Voltage Pulsing over Si-Substrate Backside of IC chips. FDTC Yusuke Hayashi, Rikuu Hasegawa, Takuya Wadatsumi, Kazuki Monta, Takuji Miki, Makoto Nagata
2024	—	`conf`	Modeling and Analysis of On-Chip Voltage Fluctuations Caused by Electromagnetic Fault Injection. EMC Compo Takuya Wadatsumi, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Lang Lin, Norman Chang, Makoto Nagata
2024	—	`conf`	On-Chip Evaluation of Voltage Drops and Fault Occurrence Induced by Si Backside EM Injection. COSADE Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata
2024	—	`conf`	Photon Emission Modeling and Machine-Learning Assisted Pre-Silicon Optical Side-Channel Simulation. HOST Henian Li, Lang Lin, Norman Chang, Sreeja Chowdhury, Dylan Mcguire, Bozidar Novakovic, Kazuki Monta, Makoto Nagata, Ying-Shiun Li, Pramod M. S, Piin-Chen Yeh, Jyh-Shing Roger Jang, Chengjie Xi, Qiutong Jin, Navid Asadi, Mark Tehranipoor
2024	—	`conf`	Si-Backside Side-Channel Leakage Measurement and Simulation. ISOCC Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Akhilesh Kumar, Norman Chang
2024	—	`conf`	Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. 3DIC Shuhei Yokota, Rikuu Hasegawa, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	—	`conf`	A Triturated Sensing System. ISSCC Noriyuki Miura, Kotaro Naruse, Jun Shiomi, Yoshihiro Midoh, Tetsuya Hirose, Takaaki Okidono, Takuji Miki, Makoto Nagata
2023	J	`jnl`	An Analog Side-Channel Attack on a High-Speed Asynchronous SAR ADC Using Dual Neural Network Technique. IEICE Trans. Electron. Ryozo Takahashi, Takuji Miki, Makoto Nagata
2023	—	`conf`	Characterization of Backside ESD Impacts on Integrated Circuits. IRPS Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kazuki Monta, Takuji Miki, Makoto Nagata
2023	J	`jnl`	Design of Circuits and Packaging Systems for Security Chips. IEICE Trans. Electron. Makoto Nagata
2023	J	`jnl`	Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging. IEICE Trans. Electron. Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata
2023	—	`conf`	Findings of the 2023 Conference on Machine Translation (WMT23): LLMs Are Here but Not Quite There Yet. WMT Tom Kocmi, Eleftherios Avramidis, Rachel Bawden, Ondrej Bojar, Anton Dvorkovich, Christian Federmann, Mark Fishel, Markus Freitag, Thamme Gowda, Roman Grundkiewicz, Barry Haddow, Philipp Koehn, Benjamin Marie, Christof Monz, Makoto Morishita, Kenton Murray, Makoto Nagata, Toshiaki Nakazawa, Martin Popel, Maja Popovic, Mariya Shmatova
2023	J	`jnl`	Guest Editorial IEEE 2022 European Solid-State Circuits Conference. IEEE J. Solid State Circuits Makoto Nagata, Massimo Alioto
2023	A*	`conf`	On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits. DAC Kazuki Monta, Makoto Nagata, Josep Balasch, Ingrid Verbauwhede
2023	J	`jnl`	Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis. ACM J. Emerg. Technol. Comput. Syst. Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata
2022	J	`jnl`	An 11-bit 0.008mm IEICE Electron. Express Takuji Miki, Ryozo Takahashi, Makoto Nagata
2022	—	`conf`	Exploring Fault Injection Attack Resilience of Secure IC Chips : Invited Paper. IRPS Makoto Nagata
2022	J	`jnl`	Physical Attack Protection Techniques for IC Chip Level Hardware Security. IEEE Trans. Very Large Scale Integr. Syst. Makoto Nagata, Takuji Miki, Noriyuki Miura
2022	J	`jnl`	Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements. IEEE Des. Test Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Takuji Miki, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
2022	—	`conf`	Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging. IRPS Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Takuji Miki, Makoto Nagata, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo
2021	—	`conf`	Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited). SLIP Makoto Nagata
2021	J	`jnl`	Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma
2021	J	`jnl`	Foreword. IEICE Trans. Electron. Makoto Nagata
2021	J	`jnl`	Landside capacitor efficacy among multi-chip-module using Si-interposer. IEICE Electron. Express Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2021	J	`jnl`	Low-cost distance-spoofing attack on FMCW radar and its feasibility study on countermeasure. J. Cryptogr. Eng. Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata
2021	—	`conf`	Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification. HOST Lang Lin, Deqi Zhu, Jimin Wen, Hua Chen, Yu Lu, Norman Chang, Calvin Chow, Harsh Shrivastav, Chia-Wei Chen, Kazuki Monta, Makoto Nagata
2021	B	`conf`	Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring. ETS Kazuki Monta, Leonidas Katselas, Ferenc Fodor, Alkis A. Hatzopoulos, Makoto Nagata, Erik Jan Marinissen
2020	J	`jnl`	A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation. IEICE Trans. Electron. Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata
2020	J	`jnl`	A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack. IEEE Trans. Circuits Syst. II Express Briefs Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	C	`conf`	A Random Interrupt Dithering SAR Technique for Secure ADC against Reference-Charge Side-Channel Attack. ISCAS Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata
2020	—	`conf`	Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis. iSES Lang Lin, Dinesh Selvakumaran, Deqi Zhu, Norman Chang, Calvin Chow, Makoto Nagata, Kazuki Monta
2020	J	`jnl`	Foreword. IEICE Trans. Electron. Makoto Nagata
2020	J	`jnl`	High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger
2020	J	`jnl`	Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. IEEE J. Solid State Circuits Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	J	`jnl`	A 0.72pJ/bit 400μm IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Makoto Nagata
2019	—	`conf`	A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar. ASHES@CCS Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, Shoei Nashimoto, Daisuke Suzuki
2019	—	`conf`	A Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. A-SSCC Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	—	`conf`	Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security - Invited Paper. SPACE Makoto Nagata
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	—	`conf`	On-Chip Physical Attack Protection Circuits for Hardware Security : Invited Paper. CICC Makoto Nagata, Takuji Miki, Noriyuki Miura
2019	—	`conf`	On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper. ASICON Makoto Nagata
2019	—	`conf`	Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. 3DIC Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi
2019	J	`jnl`	Side-channel leakage from sensor-based countermeasures against fault injection attack. Microelectron. J. Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
2018	J	`jnl`	A 286 F IEEE J. Solid State Circuits Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
2018	—	`conf`	A 286F ISSCC Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura
2018	J	`jnl`	A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto
2018	J	`jnl`	A study on substrate noise coupling among TSVs in 3D chip stack. IEICE Electron. Express Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne
2018	C	`conf`	Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata
2018	J	`jnl`	Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor. IEEE J. Solid State Circuits Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
2018	—	`conf`	Session 17 overview: Technologies for health and society: Technology directions subcommittee. ISSCC Patrick P. Mercier, Long Yan, Makoto Nagata
2018	—	`conf`	Session 21 overview: Extending silicon and its applications: Technology directions subcommittee. ISSCC Jan Genoe, Frederic Gianesello, Makoto Nagata
2018	—	`conf`	Session 30 overview: Emerging memories: Memory and technology directions subcommittees. ISSCC Shinichiro Shiratake, Edoardo Charbon, Leland Chang, Makoto Nagata
2018	—	`conf`	Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees. ISSCC Naveen Verma, Fatih Hamzaoglu, Makoto Nagata, Leland Chang
2017	—	`conf`	15.8 A permanent digital archive system based on 4F ISSCC Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata
2017	J	`jnl`	A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS. IEICE Trans. Electron. Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2017	—	`conf`	An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2017	—	`conf`	Chaos, deterministic non-periodic flow, for chip-package-board interactive PUF. A-SSCC Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata
2017	J	`jnl`	Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	C	`conf`	Exploiting Bitflip Detector for Non-invasive Probing and its Application to Ineffective Fault Analysis. FDTC Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata
2017	J	`jnl`	Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama
2016	—	`conf`	A 500MHz-BW -52.5dB-THD Voltage-to-Time Converter utilizing a two-step transition inverter. ESSCIRC Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata
2016	J	`jnl`	A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger
2016	—	`conf`	F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata
2016	—	`conf`	On-chip substrate-bounce monitoring for laser-fault countermeasure. AsianHOST Kohei Matsuda, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Tatsuya Fujii, Kazuo Sakiyama
2016	A*	`conf`	PLL to the rescue: a novel EM fault countermeasure. DAC Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
2016	C	`conf`	Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2015	J	`jnl`	A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata
2015	—	`conf`	A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2015	J	`jnl`	A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki
2015	—	`conf`	A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger
2015	J	`jnl`	An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. IEEE Trans. Very Large Scale Integr. Syst. Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
2015	—	`conf`	Analysis of on-chip digital noise coupling path for wireless communication IC test chip. EMC Compo Satoshi Tanaka, Peng Fan, Jingyan Ma, Hanae Aoki, Masahiro Yamaguchi, Makoto Nagata, Sho Muroga
2015	Misc	`conf`	At-Product-Test Dedicated Adaptive supply-resonance suppression. VTS Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
2015	A*	`conf`	EM attack sensor: concept, circuit, and design-automation methodology. DAC Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki
2015	J	`jnl`	In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking. IEEE Des. Test Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda
2015	—	`conf`	Nano-Function materials for TSV technologies. 3DIC Hiroaki Ikeda, Shigenobu Sekine, Ryuji Kimura, Koichi Shimokawa, Keiji Okada, Hiroaki Shindo, Tatsuya Ooi, Rei Tamaki, Makoto Nagata
2015	Misc	`conf`	Optimal error feedback filters for uniform quantizers at remote sensors. ICASSP Shuichi Ohno, Yuji Wakasa, Makoto Nagata
2015	—	`conf`	Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee. ISSCC Makoto Nagata, Stefano Stanzione
2014	—	`conf`	12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata
2014	J	`jnl`	A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
2014	—	`conf`	A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata
2014	—	`conf`	A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils. VLSI-DAT Taisuke Hayashi, Noriyuki Miura, Kumpei Yoshikawa, Makoto Nagata
2014	J	`jnl`	AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model. IEICE Trans. Electron. Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata
2014	—	`conf`	An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata
2014	J	`jnl`	Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator. IEICE Trans. Electron. Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
2014	J	`jnl`	Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking. IEICE Trans. Electron. Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata
2014	J	`jnl`	EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014	A	`conf`	EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki
2014	J	`jnl`	Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu
2014	—	`conf`	On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura
2014	—	`conf`	Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata
2014	J	`jnl`	Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger
2014	—	`conf`	Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger
2014	J	`jnl`	Timing margin enhancement technique for current mode interface. IEICE Electron. Express Takefumi Yoshikawa, Makoto Nagata
2013	—	`conf`	A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing. ISSCC Satoshi Takaya, Makoto Nagata, Atsushi Sakai, Takashi Kariya, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda
2013	J	`jnl`	A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
2013	J	`jnl`	Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits. IEICE Trans. Electron. Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata
2013	J	`jnl`	Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components. IEICE Trans. Electron. Naoya Azuma, Makoto Nagata
2013	—	`conf`	Immunity evaluation of inverter chains against RF power on power delivery network. EMC Compo Kumpei Yoshikawa, Yuji Harada, Noriyuki Miura, Noriaki Takeda, Yoshiyuki Saito, Makoto Nagata
2013	—	`conf`	In-band spurious attenuation in LTE-class RFIC chip using a soft magnetic thin film. EMC Compo Sho Muroga, Y. Shimada, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, Naoya Azuma, Makoto Nagata, Motoki Murakami, Kazuaki Hori, Satoru Takahashi
2013	A	`conf`	In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers. ITC Naoya Azuma, T. Makita, S. Ueyama, Makoto Nagata, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi
2013	—	`conf`	Measurement-based diagnosis of wireless communication performance in the presence of in-band interferers in RF ICs. EMC Compo Makoto Nagata, Shunsuke Shimazaki, Naoya Azuma, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Satoshi Tanaka, Masahiro Yamaguchi
2013	J	`jnl`	Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation. IEICE Trans. Electron. Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2013	—	`conf`	Measurements and simulation of substrate noise coupling in RF ICs with CMOS digital noise emulator. EMC Compo Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi
2013	—	`conf`	Noise analysis using on-chip waveform monitor in bandgap voltage references. EMC Compo Akitaka Murata, Shuji Agatsuma, Daisaku Ikoma, Kouji Ichikawa, Takahiro Tsuda, Makoto Nagata, Kumpei Yoshikawa, Yuuki Araga, Yuji Harada
2013	J	`jnl`	Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata
2013	—	`conf`	Very low-voltage swing while high-bandwidth data transmission through 4096 bit TSVs. 3DIC Satoshi Takaya, Makoto Nagata, Hiroaki Ikeda
2012	J	`jnl`	Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kumpei Yoshikawa, Yuta Sasaki, Kouji Ichikawa, Yoshiyuki Saito, Makoto Nagata
2012	J	`jnl`	Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. IEICE Trans. Electron. Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata
2012	—	`conf`	Foreword. VLSIC Ajith Amerasekera, Makoto Nagata
2012	J	`jnl`	Foreword. IEICE Trans. Electron. Makoto Nagata
2012	J	`jnl`	Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits. IEEE J. Solid State Circuits Makoto Nagata, Vivek De
2012	J	`jnl`	Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Makoto Nagata
2012	J	`jnl`	On-Chip In-Place Measurements of V IEICE Trans. Electron. Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011	J	`jnl`	A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits. IEICE Trans. Electron. Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011	J	`jnl`	A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength. IEICE Trans. Electron. Takushi Hashida, Yuuki Araga, Makoto Nagata
2011	Misc	`conf`	A diagnosis testbench of analog IP cores against on-chip environmental disturbances. VTS Takushi Hashida, Yuuki Araga, Makoto Nagata
2011	—	`conf`	A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
2011	—	`conf`	Accurate analysis of substrate sensitivity of active transistors in an analog circuit. ISQED Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2011	J	`jnl`	An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration. IEEE J. Solid State Circuits Takushi Hashida, Makoto Nagata
2011	—	`conf`	In-tier diagnosis of power domains in 3D TSV ICs. 3DIC Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
2011	J	`jnl`	Microprocessor power noise measurements with different levels of resource occupancy. IEICE Electron. Express Yoji Bando, Makoto Nagata
2011	J	`jnl`	On-Chip Single Tone Pseudo-Noise Generator for Analog IP Noise Tolerance Measurement. IEICE Trans. Electron. Masaaki Souda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata
2010	J	`jnl`	An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
2010	C	`conf`	An on-chip waveform capturing technique pursuing minimum cost of integration. ISCAS Yuuki Araga, Takushi Hashida, Makoto Nagata
2010	J	`jnl`	Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails. IEICE Trans. Electron. Takushi Hashida, Makoto Nagata
2010	J	`jnl`	Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata
2009	—	`conf`	A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata
2009	—	`conf`	A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design. CICC Daisuke Kosaka, Yoji Bando, Goichi Yokomizo, Kunihiko Tsuboi, Ying Shiun Li, Shen Lin, Makoto Nagata
2009	J	`jnl`	Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. IEICE Trans. Electron. Mitsuya Fukazawa, Masanori Kurimoto, Rei Akiyama, Hidehiro Takata, Makoto Nagata
2008	J	`jnl`	Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications. IEICE Trans. Electron. Takefumi Yoshikawa, Tetsuhiro Ogino, Makoto Nagata
2008	J	`jnl`	Measurement-Based Analysis of Electromagnetic Immunity in LSI Circuit Operation. IEICE Trans. Electron. Kouji Ichikawa, Yuki Takahashi, Yukihiko Sakurai, Takahiro Tsuda, Isao Iwase, Makoto Nagata
2008	—	`conf`	Session 13 - Biomedical, sensors and MEMS. CICC Makoto Nagata, Steven L. Garverick
2007	J	`jnl`	A Mixed Circuit and System Level Simulation Technique of Collision-Resistant RFID System. IEICE Trans. Electron. Yohei Fukumizu, Naoki Gochi, Makoto Nagata, Kazuo Taki
2007	J	`jnl`	An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration. IEEE Trans. Very Large Scale Integr. Syst. Koichiro Noguchi, Makoto Nagata
2007	J	`jnl`	Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Trans. Electron. Masao Morimoto, Makoto Nagata, Kazuo Taki
2007	J	`jnl`	Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	—	`conf`	Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. CICC Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	J	`jnl`	Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
2007	J	`jnl`	Experimental Verification of Power Supply Noise Modeling for EMI Analysis through On-Board and On-Chip Noise Measurements. IEICE Trans. Electron. Kouji Ichikawa, Yuki Takahashi, Makoto Nagata
2007	—	`conf`	Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. ISSCC Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata
2007	A*	`conf`	On-Chip Measurements Complementary to Design Flow for Integrity in SoCs. DAC Makoto Nagata
2007	J	`jnl`	On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration. IEICE Trans. Electron. Koichiro Noguchi, Takushi Hashida, Makoto Nagata
2007	—	`conf`	On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. ISSCC Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata
2007	J	`jnl`	Substrate-Noise and Random-Variability Reduction with Self-Adjusted Forward Body Bias. IEICE Trans. Electron. Yoshihide Komatsu, Koichiro Ishibashi, Makoto Nagata
2006	—	`conf`	A built-in power supply noise probe for digital LSIs. ASP-DAC Mitsuya Fukazawa, Koichiro Noguchi, Makoto Nagata, Kazuo Taki
2006	J	`jnl`	An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Trans. Electron. Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa
2006	J	`jnl`	An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity. IEICE Trans. Electron. Koichiro Noguchi, Makoto Nagata
2006	J	`jnl`	Back-End Design of a Collision-Resistive RFID System through High-Level Modeling Approach. IEICE Trans. Electron. Yohei Fukumizu, Makoto Nagata, Kazuo Taki
2006	J	`jnl`	Communication Scheme for a Highly Collision-Resistive RFID System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yohei Fukumizu, Shuji Ohno, Makoto Nagata, Kazuo Taki
2006	—	`conf`	Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform. CICC Mitsuya Fukazawa, Makoto Nagata
2006	—	`conf`	Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation. ASP-DAC Daisuke Kosaka, Makoto Nagata
2006	J	`jnl`	Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. IEICE Trans. Electron. Mitsuya Fukazawa, Makoto Nagata
2006	J	`jnl`	Multi-Ported Register File for Reducing the Impact of PVT Variation. IEICE Trans. Electron. Yuuichirou Ikeda, Masaya Sumita, Makoto Nagata
2006	J	`jnl`	Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation. Proc. IEEE Ali Afzali-Kusha, Makoto Nagata, Nishath K. Verghese, David J. Allstot
2005	J	`jnl`	A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2005	J	`jnl`	A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits. IEEE J. Solid State Circuits Makoto Nagata, Takeshi Okumoto, Kazuo Taki
2005	—	`conf`	An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. CICC Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa
2005	—	`conf`	An on-chip multi-channel waveform monitor for mixed-signal VLSI diagnostics. ESSCIRC Koichiro Noguchi, Makoto Nagata
2005	J	`jnl`	Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits. IEICE Trans. Electron. Kenji Shimazaki, Makoto Nagata, Takeshi Okumoto, Shozo Hirano, Hiroyuki Tsujikawa
2005	J	`jnl`	High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Trans. Electron. Masao Morimoto, Makoto Nagata, Kazuo Taki
2005	J	`jnl`	Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki
2005	A	`conf`	On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. DATE Koichiro Noguchi, Makoto Nagata
2005	—	`conf`	Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. CICC Yoshihide Komatsu, Koichiro Ishibashi, Masaharu Yamamoto, Toshiro Tsukada, Kenji Shimazaki, Mitsuya Fukazawa, Makoto Nagata
2004	—	`conf`	Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement. CICC Shen Lin, Makoto Nagata, Kenji Shimazaki, Kazuhiro Satoh, Masaya Sumita, Hiroyuki Tsujikawa, Andrew T. Yang
2003	—	`conf`	A substrate noise analysis methodology for large-scale mixed-signal ICs. CICC Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto
2002	—	`conf`	A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
2002	J	`jnl`	Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata
2002	—	`conf`	Modeling substrate noise generation in CMOS digital integrated circuits. CICC Makoto Nagata, Takashi Morie, Atsushi Iwata
2002	—	`conf`	Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. ASP-DAC/VLSI Design Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata
2001	—	`conf`	An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
2001	—	`conf`	Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
2001	J	`jnl`	Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata
2001	—	`conf`	Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	—	`conf`	A smart imager for the vision processing front-END. ASP-DAC Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
2000	—	`conf`	An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
2000	J	`jnl`	Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	C	`conf`	Pulse modulation circuit architecture and its application to functional image sensors. ISCAS Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie
2000	—	`conf`	Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
2000	—	`conf`	Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC Makoto Nagata, Atsushi Iwata
1999	—	`conf`	A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
1999	—	`conf`	Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata
1998	J	`jnl`	A PWM signal processing core circuit based on a switched current integration technique. IEEE J. Solid State Circuits Makoto Nagata, Jun Funakoshi, Atsushi Iwata
1998	B	`conf`	Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
1998	B	`conf`	Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata