Mahyar Emami

12 papers A* 1A 3B 2Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2025 — conf
Parendi: Thousand-Way Parallel RTL Simulation.
ASPLOS (2)
Mahyar Emami, Thomas Bourgeat, James R. Larus
2024 A conf
A 475 MHz Manycore FPGA Accelerator for RTL Simulation.
FPGA
Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus
2024 — —
Highly Parallel RTL Simulation.
Mahyar Emami
2024 J jnl
Parendi: Thousand-Way Parallel RTL Simulation.
CoRR
Mahyar Emami, Thomas Bourgeat, James R. Larus
2024 A* conf
Performance Interfaces for Hardware Accelerators.
OSDI
Jiacheng Ma, Rishabh R. Iyer, Sahand Kashani, Mahyar Emami, Thomas Bourgeat, George Candea
2023 — conf
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism.
ASPLOS (4)
Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus
2023 J jnl
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism.
CoRR
Mahyar Emami, Sahand Kashani, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus
2022 B conf
Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks.
PACT
Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
2022 B conf
Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats.
FPL
Sahand Kashani, Mahyar Emami, James R. Larus
2021 J jnl
StreamBlocks: A compiler for heterogeneous dataflow computing (technical report).
CoRR
Endri Bezati, Mahyar Emami, Jörn W. Janneck, James R. Larus
2021 A conf
Triggered Scheduling: Efficient Detection of Dataflow Network Idleness on Heterogeneous Systems.
FPGA
Mahyar Emami, Endri Bezati, Jörn W. Janneck, James R. Larus
2020 A conf
Advanced Dataflow Programming using Actor Machines for High-Level Synthesis.
FPGA
Endri Bezati, Mahyar Emami, James R. Larus